Kevin Skadron's and the LAVA Lab's Research Papers

Publications by Kevin Skadron and the LAVA Lab

Please note that papers linked here represent author preprints. The official, published version must be obtained from the publisher's website or the published print copy. This material is presented here to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each document's copyright terms. In most cases, these works may not be reposted without the explicit permission of the copyright holder. Permission is given to make digital or hard copies of all or part of this material without fee for personal or classroom use, provided that the copies are not made or distributed for profit or commercial advantage, and that copies bear the appropriate copyright notice and the full bibliographic citation on the first page. Copyrights for components of this work owned by others must also be honored. To copy otherwise, to republish, to post on servers, to redistribute to lists, etc. requires specific permission and/or a fee. In particular, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works, must be obtained from the copyright owner.

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(Link to U.Va. Library for archive of U.Va.-CS technical reports)

Automata Processing

MNRL - a specification language for finite state machines
MNCaRT - an end-to-end research toolkit for automata processing across multiple processing platforms

ATR - Automata-to-routing - an adaptation of VPR for automata processing on spatial architectures

VASim - An engine for cross-platform automata processing, supporting CPU, FGPA, Micron AP, and coming soon, GPU
iNFAnt2 - a GPU NFA execution engine
ANMLZoo - A benchmark suite for automata processing
RAPID - a C-like programming language for inexact pattern matching
T. Xie, V. Dang, J. Wadden, K. Skadron, and M. R. Stan. “REAPR: Reconfigurable Engine for Automata Processing.” In Proceedings of the International Conference on Field-Programmable Logic and Applications (FPL), Sept. 2017, to appear. (pdf)
Q. Wang, M. El-Hadedy, K. Skadron, and K. Wang. “Accelerating Weeder: A DNA Motif Search Tool using the Micron Automata Processor and FPGA.” IEICE Transactions on Information and Systems, to appear. (preprint pdf)
K. Angstadt, J. P. Wadden, W. Weimer, and K. Skadron. "MNRL and MNCaRT: An Open-Source, Multi-Architecture State Machine Research and Execution Ecosystem." Tech. Report CS-2017-01, Univ. of Virginia Dept. of Computer Science, May 2017. (pdf)
K. Wang, E. Sadredini, and K. Skadron. "Hierarchical Pattern Mining with the Automata Processor." International Journal of Parallel Programming, Springer, published online Jan. 2017. DOI:10.1007/s10766-017-0489-y (preprint pdf)
E. Sadredini, K. Wang, and K. Skadron. “Frequent Subtree Mining on the Automata Processor: Challenges and Opportunities.” In Proceedings of the ACM International Conference on Supercomputing (ICS), June 2017. (pdf)
J. Wadden, Samira Khan, and K. Skadron. “Automata-to-Routing: An Open-Source Toolchain for Design-Space Exploration of Spatial Automata Processing Architectures.” In Proceedings of the IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM), Apr. 2017. (pdf)
C. Bo, K. Wang, J. Fox, and K. Skadron. “Entity Resolution Acceleration using Micron’s Automata Processor. In Proceedings of the 2016 IEEE International Conference on Big Data (BigData), Dec. 2016. (pdf)
T. Ly, R. Sarkar, K. Skadorn, and S. T. Acton. “Feature Extraction and Image Retrieval on an Automata Structure.” In Proceedings of the 50th Asilomar Conference on Signals, Systems and Computers, Nov. 2016. (pdf)
J. P. Wadden, N. Brunelle, G. Robins, and K. Skadron. “Generating Efficient and High-Quality Pseudo-Random Behavior on Micron’s Automata Processor.” In Proceedings of the IEEE International Conference on Computer Design (ICCD), Oct. 2016. (pdf)
K. Wang, K. Angstadt, C. Bo, N. Brunelle, E. Sadredini, T. Tracy II, J. Wadden, M. R. Stan, and K. Skadron. “An Overview of Micron’s Automata Processor.” In Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), Oct. 2016. (pdf)
J. P. Wadden, V. Dang, N. Brunelle, T. Tracy II, D. Guo, E. Sadredini, K. Wang, C. Bo, G. Robins, M. R. Stan, and K. Skadron. “ANMLZoo: A Benchmark Suite for Exploring Bottlenecks in Automata Processing Engines and Architectures.” In Proceedings of the IEEE International Symposium on Workload Characterization (IISWC), Sept. 2016. (pdf)
K. Wang, E. Sadredini, and K. Skadron. “Sequential Pattern Mining with the Micron Automata Processor.” In Proceedings of the ACM International Conference on Computing Frontiers, May 2016. Best paper award! (pdf)
K. Angstadt, W. Weimer, and K. Skadron. "RAPID Programming of Pattern-Recognition Processors." In Proceedings of the ACM International Symposium on Architectural Support for Programming Languages and Operating Systems (ASPLOS), Apr. 2016. (pdf | software)

K. Zhou, J. Wadden, J. J. Fox, K. Wang, D. E. Brown, and K. Skadron. “Regular Expression Acceleration on the Micron Automata Processor: Brill Tagging as a Case Study.” In Proceedings of the IEEE International Conference on Big Data (BigData), Oct. 2015. (pdf)

D. Guo, N. Brunelle, C. Bo, K. Wang, and K. Skadron. "Subset Encoding: Increasing Pattern Density for Finite Automata." Tech. Report CS-2015-07, Univ. of Virginia Dept. of Computer Science, July 2017. (pdf)

C. Bo, K. Wang, J. Fox, and K. Skadron. “Entity Resolution Acceleration using Automata Processor.” In Proceedings of the 5th International Workshop on Architectures and Systems for Big Data (ASBD), in conjunction with ISCA, June 2015. (pdf)

T. Tracy, M. Stan, N. Brunelle, J. Wadden, K. Wang, K. Skadron, and G. Robins. “Nondeterministic Finite Automata in Hardware – the Case of the Levenshtein Automaton.” In Proceedings of the 5th International Workshop on Architectures and Systems for Big Data (ASBD), in conjunction with ISCA, June 2015. (pdf)

K. Wang and K. Skadron. "Cellular Automata on the Micron Automta Processor." Tech. Report CS-2015-03, Univ. of Virginia Dept. of Computer Science, Apr. 2015. (pdf)

K. Wang, J. Qi, J. J. Fox, M. R. Stan, and K. Skadron. "Association Rule Mining with the Micron Automata Processor." In Proceedings of the IEEE International Parallel and Distributed Processing Symposium, May 2015. (pdf)

K. Zhou, J. J. Fox, K. Wang, D. E. Brown, and K. Skadron. "Brill Tagging on the Micron Automata Processor." In Proceedings of the 2015 IEEE International Conference on Semantic Computing, Feb. 2015. (pdf)

Multi-core, Many-core, Multi-threading, Heterogeneous Architectures, and SIMD Organization

Rodinia Benchmarks Wiki - now version 2.4!

MV5 simulator - a modification of M5 supporting SIMD and multithreaded architectures

V. Dang and K. Skadron. “Acceleration of Frequent Itemset Mining on FPGA Using SDAccel and Vivado HLS.” In Proceedings of the IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), July 2017. (pdf)

M. El-Hadedy, X. Guo, M. R. Stan, and K. Skadron. “PPE-ARX: Area- and Power-Efficient VLIW Programmable Processing Element for IoT Crypto-Systems.” Poster and paper, in Proceedings of the NASA/ESA Conference on Adaptive Hardware Systems (AHS), July 2017. (pdf)

M. El-Hadedy, A. Kulkarni, D. Stroobandt, and K. Skadron. “Reco-Pi: A Reconfigurable Cryptoprocessor for Pi-Cipher.” Journal of Parallel and Distributed Computing, Elsevier, published online May 2017. DOI: 10.1016/j.jpdc.2017.05.012.

L. Wang and K. Skadron. “Dark vs. Dim Silicon and Near-Threshold Computing.” In The Dark Side of Silicon (Computing in the Dark Silicon Era), edited by A. Rahamani, P. Liljeberg, A. Jantsch, and H. Tenhunen. Springer, 2017.

L. Wang and K. Skadron. “Lumos+: Rapid, Pre-RTL Design Space Exploration on Accelerator-Rich Heterogeneous Architectures with Reconfigurable Logic.” In Proceedings of the IEEE International Conference on Computer Design (ICCD), Oct. 2016. (pdf)

M. El-Hadedy, X. Guo, M. Margala, M. R. Stan, and K. Skadron. “Dual-Data Rate Transpose-Memory Architecture Improves the Performance, Power and Area of Signal-Processing Systems.” Journal of Signal Processing Systems, Springer, published online Nov. 2016. DOI 10.1007/s11265-016-1199-1.

M. El-Hadedy, H. Mihajloska, D. Gligoroski, A. Kulkarni, D. Stroobandt and K. Skadron. “A 16-bit Reconfigurable Encryption Processor for Pi-Cipher.” In Proceedings of the 23rd Reconfigurable Architectures Workshop (RAW), in conjunction with IPDPS, May 2016. Best paper award! (pdf)

L. Wang. "First-Order Modeling Frameworks for Power-Efficient and Reliable Multiprocessor Systems." PhD dissertation, Univ. of Virginia School of Engineering and Applied Science, May 2016. (pdf)

M. El-Hadedy, D. Patel, M. Margala, and K. Skadron. “Area-Speed-Efficient Transpose-Memory Architecture for Signal-Processing Systems.” In Proceedings of the 10th HIPEAC Workshop on Reconfigurable Computing (WRC), Jan. 2016. (pdf)

M. El-Hadedy and K. Skadron. “Hardware Overhead Analysis of Programmability in ARX Crypto Processing.” In Proceedings of the Workshop on Hardware and Architectural Support for Security and Privacy (HASP), in conjunction with ISCA, June 2015. (pdf)

S. Che, J. Meng, and K. Skadron. "Dymaxion++: A Directive-based API to Optimize Data Layout and Memory Mapping for Heterogeneous Systems." In Proceedings of the Fourth International Workshop on Accelerators and Hybrid Exascale Systems, in conjunction with IPDPS, May 2014. (pdf)

S. Arrabi, D. Moore, L. Wang, K. Skadron, B. H. Calhoun, J. Lach, and B. H. Meyer. " Flexibility and Energy Trade-offs in Reconfigurable MIMD/SIMD Systems." Abstract and poster, IEEE International Symposium on Field-Programmable Custom Computing Machines, May 2014. (abstract | poster)

L. Wang and K. Skadron. "Implications of the Power Wall: Dim Cores and Reconfigurable Logic." IEEE Micro special issue on Dark Silicon, 33(5): 40-49, Sept.-Oct. 2013. DOI 10.1109/MM.2013.74. (preprint pdf | Lumos software)

L. Szafaryn, T. Gamblin, B. R. de Supinski, and K. Skadron. "Trellis: Portability Across Architectures with a High-level Framework." Elsevier Journal of Parallel and Distributed Computing, 73(10):1400-13, Oct. 2013. (First published online July, 2013.) DOI 10.1016/j.jpdc.2013.07.001. (preprint pdf)

S. Che. B. M. Beckmann, S. K. Reinhardt, and K. Skadron, "Pannotia: A Characterization of GPGPU Graph Applications, In Proceedings of the IEEE International Symposium on Workload Characterization (IISWC), Sept. 2013. (pdf)

J. Meng, J. W. Sheaffer, and K. Skadron. "Robust SIMD: Dynamically Adapted SIMD Width and Multi-Threading Depth." In Proceedings of the IEEE International Parallel & Distributed Processing Symposium (IPDPS), May 2012. (pdf)

M. Gebhart, D. R. Johnson, D. Tarjan, S. W. Keckler, W. J. Dally, E. Lindholm, and K. Skadron. " A Hierarchical Thread Scheduler and Register File for Energy-efficient Throughput Processors." ACM Transactions on Computer Systems (TOCS), 30(2), 38 pages, Apr. 2012. DOI 10.1145/2166879.2166882. (preprint pdf)

J. Yang, K. Whitehouse, K. Skadron, and M. L. Soffa. "Potential of Dynamic Binary Parallelization." In Proceedings of the 7th International Workshop on Unique Chips and Systems (UCAS-7), in conjunction with HPCA, Feb. 2012.

J. W. Sheaffer and K. Skadron. "Fractal: A Software Toolchain for Mapping Applications to Diverse, Heterogeneous Architectures." Tech. Report CS-2011-09, Univ. of Virginia Dept. of Computer Science, Dec. 2011. (pdf)

S. Che, J. W. Sheaffer, and K. Skadron. "Dymaxion: Optimizing Memory Access Patterns for Heterogeneous Systems." In Proceedings of the ACM/IEEE International Conference for High Performance Computing, Networking, Storage and Analysis (SC), Nov. 2011. (pdf)

W. Huang, K. Rajamani, M. R. Stan, and K. Skadron. "Scaling with Design Constraints – Predicting the Future of Big Chips." IEEE Micro special issue on Big Chips, 31(4):16-29, July/Aug. 2011, DOI 10.1109/MM.2011.42. (preprint pdf)

M. Boyer, S. Che, K. Skadron, J. Gummaraju, and N. Jayasena. "Automatic, Intra-Application Load Balancing for Heterogeneous Systems." Presentation at the AMD Fusion Developers Summit, June 2011. (slides pdf)

M. Gebhart, D. R. Johnson, D. Tarjan, S. W. Keckler, W. J. Dally, E. Lindholm, and K. Skadron. "Energy-efficient Mechanisms for Managing Thread Context in Throughput Processors." In Proceedings of the ACM/IEEE International Symposium on Computer Architecture (ISCA), June 2011. (pdf)

C. Gregg, M. Boyer, K. Skadron, and K. Hazelwood. "Dynamic Heterogeneous Scheduling Decisions Using Historical Runtime Data." In Proceedings of the 2nd Workshop on Applications for Multi and Many Core Processors: Analysis, Implementation, and Performance (A4MMC), in conjunction with ISCA, June 2011. (pdf)

L. Szafaryn, T. Gamblin, B. de Supinski, and K. Skadron. "Experiences with Achieving Portability across Heterogeneous Architectures." In Proceedings of the First International Workshop on Domain-Specific Languages and High-Level Frameworks for High Performance Computing (WOLFHPC), in conjunction with ICS, May 2011. (pdf | software)

J. Yang, K. Skadron, M. L Soffa and K. Whitehouse. “Feasibility of Dynamic Binary Parallelization.” In Proceedings of the 3rd USENIX Workshop on Hot Topics in Parallelism (HotPar), 8 pages, May 2011. Poster presentation with accompanying proceedings paper. (paper pdf)

M. Boyer, D. Tarjan, K. Skadron. “Federation: Boosting Per-Thread Performance of Throughput-Oriented Manycore Architectures.” ACM Transactions on Architecture and Code Optimization (TACO), 7(4):1-38, Dec. 2010, DOI 10.1145/1880043.1880046. (preprint pdf)

S. Che, J. W. Sheaffer, M. Boyer, L. G. Szafaryn, L. Wang, and K. Skadron. "A Characterization of the Rodinia Benchmark Suite with Comparison to Contemporary CMP Workloads." In Proceedings of the IEEE International Symposium on Workload Characterization (IISWC), Dec. 2010. (pdf)

D. Tarjan and K. Skadron. "The Sharing Tracker: Using Ideas from Cache Coherence Hardware to Reduce Off-Chip Memory Traffic with Non-Coherent Caches." In Proceedings of the ACM/IEEE International Conference for High Performance Computing, Networking, Storage and Analysis (SC), Nov. 2010. (pdf)

J. Meng. "Breaking the Memory Wall for Highly Multi-Threaded Cores." PhD dissertation, Univ. of Virginia School of Engineering and Applied Science, Aug. 2010. Available in pdf.

J. Meng and K. Skadron. "A Performance Study for Iterative Stencil Loops on GPUs with Ghost Zone Optimizations." International Journal of Parallel Programming, Springer, 39(1):115-42, Jan. 2011. (First published online June 2010.) DOI 10.1007/s10766-010-0142-5. (preprint pdf)

J. Meng, D. Tarjan, and K. Skadron. "Dynamic Warp Subdivision for Integrated Branch and Memory Divergence Tolerance: Extended Tradeoff Analysis." Tech. Report CS-2010-5, Univ. of Virginia Dept. of Computer Science, July 2010. (pdf)

J. Meng, D. Tarjan, and K. Skadron. "Dynamic Warp Subdivision for Integrated Branch and Memory Divergence Tolerance." In Proceedings of the 37th ACM/IEEE International Symposium on Computer Architecture, June 2010. (pdf)

J. Meng, J. W. Sheaffer, and K. Skadron. "Exploiting Inter-thread Temporal Locality for Chip Multithreading." In Proceedings of the IEEE International Parallel & Distributed Processing Symposium (IPDPS), Apr. 2010. (pdf)

W. Huang, K. Skadron, S. Gurumurthi, R. J. Ribando, and M. R. Stan. "Exploring the Thermal Impact on Manycore Processor Performance." In Proceedings of the IEEE Semiconductor Thermal Measurement, Modeling, and Management Symposium (Semi-Therm 26), Feb. 2010. (pdf)

D. Tarjan, J. Meng, and K. Skadron. "Increasing Memory Miss Tolerance for SIMD Cores." In Proceedings of the ACM/IEEE International Conference for High Performance Computing, Networking, Storage and Analysis (SC), Nov. 2009. Selected as best student paper! (pdf)

S. Che, M. Boyer, J. Meng, D. Tarjan, J. W. Sheaffer, S.-H. Lee, and K. Skadron. “Rodinia: A Benchmark Suite for Heterogeneous Computing.” In Proceedings of the IEEE International Symposium on Workload Characterization (IISWC), pp. 44-54, Oct. 2009. (pdf)

J. Meng and K. Skadron “Avoiding Cache Thrashing due to Private Data Placement in Last-Level Cache for Manycore Scaling.” In Proceedings of the IEEE International Conference on Computer Design (ICCD), pp. 282-88, Oct. 2009. (pdf)

D. Tarjan. "Efficient Throughput Cores for Asymmetric Manycore Processors." PhD dissertation, Univ. of Virginia School of Engineering and Applied Science, Aug. 2009. (pdf)

J. Meng and K. Skadron. "Performance Modeling and Automatic Ghost Zone Optimization for Iterative Stencil Loops on GPUs." In Proceedings of the 23rd Annual ACM International Conference on Supercomputing (ICS), pp. 256-65, June 2009. (pdf)

M. Boyer, D. Tarjan, S. T. Acton, and K. Skadron. "Accelerating Leukocyte Tracking using CUDA: A Case Study in Leveraging Manycore Coprocessors." In Proceedings of the 23rd IEEE International Parallel and Distributed Processing Symposium (IPDPS), May 2009. (paper | slides)

J. Meng, D. Tarjan, and K. Skadron. “Leveraging Memory Level Parallelism Using Dynamic Warp Subdivision.” Tech. Report CS-2009-02, Univ. of Virginia Dept. of Computer Science, Apr. 2009. (pdf)

S. Che, M. Boyer, J. Meng, D. Tarjan, J. W. Sheaffer, and K. Skadron. "A Performance Study of General Purpose Applications on Graphics Processors using CUDA." Journal of Parallel and Distributed Computing, Elsevier, online June 2008, DOI http://dx.doi.org/10.1016/j.jpdc.2008.05.014. (UVA final preprint pdf | published pdf)

S. Che, J. Li, J. W. Sheaffer, K. Skadron, and J. Lach. “Accelerating Compute Intensive Applications with GPUs and FPGAs.” In Proceedings of the IEEE Symposium on Application Specific Processors (SASP), pp. 101-07, June 2008. (pdf)

D. Tarjan, M. Boyer, and K. Skadron. “Federation: Repurposing Scalar Cores for Out-of-Order Instruction Issue.” In Proceedings of the ACM/IEEE Conference on Design Automation (DAC), June 2008. (pdf)

W. Huang, M. R. Stan, K. Sankaranarayanan, Robert J. Ribando, and K. Skadron. “Many-Core Design from a Thermal Perspective.” In Proceedings of the ACM/IEEE Conference on Design Automation (DAC), June 2008. (pdf)

J. Meng, S. Che, J. W. Sheaffer, J. Li, J. Huang and K. Skadron. "Hierarchical Domain Partitioning For Hierarchical Architectures." Tech. Report CS-2008-05, Univ. of Virginia Dept. of Computer Science, June 2008. (pdf)

W. Huang, M. R. Stan, K. Sankaranarayanan, R. J. Ribando, and K. Skadron. "Many-Core Design from a Thermal Perspective: Extended Analysis and Results." Tech. Report CS-2008-05, Univ. of Virginia Dept. of Computer Science, Apr. 2008. (pdf)

J. Nickolls, I. Buck, M. Garland, K. Skadron. “Scalable Parallel Programming with CUDA.” ACM Queue, 6(2):40-53, Mar.-Apr. 2008. DOI 10.1145/1365490.1365500 (pdf)

D. Tarjan and K. Skadron. “Multithreading vs. Streaming” Position paper in Proceedings of the SIGPLAN Workshop on Memory Systems Performance and Correctness, Mar. 2008. (pdf)

S. Che, J. Li, J. W. Sheaffer, K. Skadron, and J. Lach. "Accelerating Compute Intensive Applications with Accelerators." Tech. Report CS-2008-04, Univ. of Virginia Dept. of Computer Science, Feb. 2008.

J. Meng, S. R. Tarapore, S. Che, J. Huang, J. W. Sheaffer, and K. Skadron. "Programming with Relaxed Streams." Tech. Report CS-2007-17, Univ. of Virginia Dept. of Computer Science, Dec. 2007. (pdf)

D. Tarjan, M. Boyer, and K. Skadron. "Federation: Out-of-Order Execution using Simple In-Order Cores." Univ. of Virginia Dept. of Computer Science Tech. Report CS-2007-11, Aug. 2007. (pdf)

E. Humenay, D. Tarjan, and K. Skadron. "Impact of Process Variations on Multicore Performance Symmetry." In Proceedings of the 2007 Conference on Design, Automation and Test in Europe, pp. 1653-58, Apr. 2007. (pdf)

E. Humenay. "Impact of Systematic Variations on Performance Symmetry in Multi-core Chips." MCS project, Univ. of Virginia School of Engineering and Applied Science, Jan. 2007.

Y. Li, K. Skadron, B. C. Lee, and D. Brooks. “Quantifying Latency and Throughput Compromises in CMP Designs.” Tech Report CS-2006-26, Univ. of Virginia Dept. of Computer Science, Dec. 2006. (pdf)

Y. Li. "Physically Constrained Chip Multiprocessor Architecture." PhD dissertation, Univ. of Virginia School of Engineering and Applied Science, Aug. 2006. Available in pdf

E. Humenay, D. Tarjan, and K. Skadron. “Impact of Parameter Variations on Multi-Core Chips.” In Proceedings of the 2006 Workshop on Architectural Support for Gigascale Integration, in conjunction with the 33rd International Symposium on Computer Architecture (ISCA), June 2006. (pdf)

Y. Li, B. Lee, D. Brooks, Z. Hu, and K. Skadron. “Impact of Thermal Constraints on Multi-Core Architectures.” In Proceedings of the IEEE/ASME Tenth Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITHERM), June 2006. (pdf).

K. Skadron. “Thermal Challenges in Architecting Multi-Core Chips,” position paper for a panel on “Challenges in Chip/Processor Level Thermal Engineering,” organized by M. Asheghi and D. Agonafer. In Proceedings of the IEEE/ASME Tenth Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITHERM), June 2006.

Y. Li, B. C. Lee, D. Brooks, Z. Hu, and K. Skadron. "CMP Design Space Exploration Subject to Physical Constraints." In Proceedings of the Twelfth IEEE International Symposium on High Performance Computer Architecture (HPCA), pp. 15-26, Feb. 2006. (pdf)

Y. Li, K. Skadron, Z. Hu, and D. Brooks. “Performance, Energy, and Thermal Considerations for SMT and CMP Architectures.” Proceedings of the Eleventh IEEE International Symposium on High Performance Computer Architecture (HPCA), Feb. 2005. Available in pdf

Y. Li, Z. Hu, D. Brooks, and K. Skadron. “Performance, Energy and Thermal Considerations for SMT and CMP Architectures: Extended Discussion and Results.” Tech Report CS-2004-32, Univ. of Virginia Dept. of Computer Science, Nov. 2004. (Extended version of HPCA-11 paper.)

Y. Li, K. Skadron, Z. Hu, and D. Brooks. “Evaluating the Thermal Efficiency of SMT and CMP Architectures.” In the IBM Watson Conference on Interaction between Architecture, Circuits, and Compilers, external track, Oct. 2004. (Also published as IBM TJ Watson Research Report RC23281, July 2004.) Available in pdf

Y. Li. "Understanding the Energy Efficiency of Simultaneous Multithreading." MCS project, Univ. of Virginia School of Engineering and Applied Science, June 2004.

K. R. Hirst, J. W. Haskins, Jr., and K. Skadron. “dMT: Inexpensive Throughput Enhancement in Small-Scale Embedded Microprocessors with Differential Multithreading.” IEE Proceedings on Computers and Digital Techniques, 151(1):43-50, Jan. 2004. Available in pdf.

K. R. Hirst, J. W. Haskins Jr., K. Skadron. "dMT: Inexpensive Throughput Enhancement in Small-Scale Embedded Microprocessors with Differential Multithreading: Extended Results." Tech Report CS-2003-18, Univ. of Virginia Dept. of Computer Science, Oct. 2003.

J.W. Haskins, Jr., K.R. Hirst, and K. Skadron. "Inexpensive Throughput Enhancement in Small-Scale Embedded Microprocessors with Block Multithreading: Extensions, Characterization, and Tradeoffs." In Proceedings of the 20th IEEE International Performance, Computing, and Communications Conference, pp. 319-28, Apr. 2001. Available in postscript (Abstract)

J.W. Haskins, Jr. and K. Skadron. "Differential Multithreading: Recapturing Pipeline Stall Cycles and Enhancing Throughput in Small-Scale Embedded Microprocessors." In Proc. of the Workshop on Complexity-Effective Design, in conjunction with ISCA-27, June 2000. Available in postscript (Abstract)

Thermal

HotSpot software home page
K. Wang, K. Skadron, and M. R. Stan. “ Closing the Power Delivery/Heat Removal Cycle for Heterogeneous Multi-Scale Systems.” In Proceedings of the 22nd International Workshop on Thermal Investigations of ICs (THERMINIC), Sept. 2016 (pdf).

R. Zhang, M. R. Stan, and K. Skadron. "HotSpot 6.0: Validation, Acceleration and Extension." Tech. Report CS-2015-04, Univ. of Virginia Dept. of Computer Science, May 2015. (pdf)
K. Sankaranarayanan, B. H. Meyer, W. Huang, R. J. Ribando, H. Haj-Hajiri, M. R. Stan, and K. Skadron. "Architectural Implications of Spatial Thermal Filtering." Elsevier Integration, the VLSI Journal, 46(1):44-56, Jan. 2013. DOI 10.1016/j.vlsi.2011.12.002 (preprint pdf)
K. Sankaranarayanan, B. H. Meyer, M. R. Stan, and K. Skadron. "Thermal Benefit of Multi-core Floorplanning: A Limits Study." Elsevier Journal of Sustainable Computing, Informatics and Systems (SUSCOM), 1(4):286-93, Dec. 2011. (First published online July 2011.) DOI 10.1016/j.suscom.2011.06.003. (preprint pdf)
J. Kong, S. W. Chung, and K. Skadron. "Recent Thermal Management Techniques for Microprocessors." ACM Computing Surveys (CSUR), 44(3), 42 pp., June 2012. (preprint pdf).
W. Huang, K. Rajamani, M. R. Stan, and K. Skadron. "Scaling with Design Constraints – Predicting the Future of Big Chips." IEEE Micro special issue on Big Chips, 31(4):16-29, July/Aug. 2011, DOI 10.1109/MM.2011.42. (preprint pdf)
W. Huang, M. Allen-Ware, J. B. Carter, E. Cheng, K. Skadron, and M. R. Stan. "Temperature-Aware Architecture: Lessons and Opportunities." Prolegomenon column in IEEE Micro, 31(3): 82-86, May/June 2011, DOI 10.1109/MM.2011.60. (preprint pdf)
Z. Qi, B. H. Meyer, W. Huang, R. J. Ribando, K. Skadron, and M. R. Stan. "Temperature-to-Power Mapping." In Proceedings of the IEEE International Conference on Computer Design (ICCD), Oct. 2010. (pdf)
W. Huang, M. R. Stan, and K. Skadron. “Thermal Modeling for Processors and Systems-on-Chip.” Chapter in Processor, Multi-Core, and System-on-Chip Simulation, edited by O. Temam and R. Leupers. Springer, 2010.

W. Huang, K. Skadron, S. Gurumurthi, R. J. Ribando, and M. R. Stan. "Exploring the Thermal Impact on Manycore Processor Performance." In Proceedings of the IEEE Semiconductor Thermal Measurement, Modeling, and Management Symposium (Semi-Therm 26), Feb. 2010. (pdf)
W. Huang, M. R. Stan, S. Gurumurthi, R. J. Ribando, and K. Skadron. "Interaction of Scaling Trends in Processor Architecture and Cooling." In Proceedings of the IEEE Semiconductor Thermal Measurement, Modeling, and Management Symposium (Semi-Therm 26), Feb. 2010. (pdf)
J. S. Lee, K. Skadron, and S. W. Chung. “Predictive Temperature-Aware DVFS.” IEEE Transactions on Computers, 59(1):127-33, Jan. 2010. DOI 10.1109/TC.2009.136. (pdf)
K. Sankaranarayanan. "Thermal Modeling and Management of Microprocessors." PhD dissertation, Univ. of Virginia School of Engineering and Applied Science, May 2009. Available in pdf.
W. Huang, K. Skadron, S. Gurumurthi, R. J. Ribando, and M. R. Stan. " Differentiating the Roles of IR Measurement and Simulation for Power and Temperature-Aware Design." In Proceedings of the 2009 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), pp. 1-10, Apr. 2009. (pdf)
K. Sankaranarayanan, M. R. Stan, and K. Skadron. “A Discussion on the Thermal Benefit of Multicore Floorplanning at the Microarchitectural Level.” Tech. Report CS-2009-04, Univ. of Virginia Dept. of Computer Science, April 2009. (pdf)
K. Sankaranarayanan, W. Huang, M. R. Stan, H. Haj-Hariri, R. J. Ribando, and K. Skadron. “Granularity of Microprocessor Thermal Management: A Technical Report.” Tech. Report CS-2009-03, Univ. of Virginia Dept. of Computer Science, April 2009. (pdf)
W. Huang, K. Sankaranarayanan, K. Skadron, R. J. Ribando, and M. R. Stan. "Accurate, Pre-RTL Temperature-Aware Processor Design Using a Parameterized, Geometric Thermal Model." IEEE Transactions on Computers, 57(9):1277-88, Sept. 2008, DOI 10.1109/TC.2008.64. (pdf)
W. Huang, M. R. Stan, K. Sankaranarayanan, Robert J. Ribando, and K. Skadron. “Many-Core Design from a Thermal Perspective.” In Proceedings of the ACM/IEEE Conference on Design Automation (DAC), June 2008. (pdf)
W. Huang, M. R. Stan, K. Sankaranarayanan, R. J. Ribando, and K. Skadron. "Many-Core Design from a Thermal Perspective: Extended Analysis and Results." Tech. Report CS-2008-05, Univ. of Virginia Dept. of Computer Science, Apr. 2008. (pdf)
K. Skadron, P. Bose, K. Ghose, R. Sendag, J. J. Yi, and D. Chiou. "Low-Power Design and Temperature Management." IEEE Micro, 27(6):46-57, Nov.-Dec. 2007. DOI 10.1109/MM.2007.104. (pdf)
J. W. Sheaffer. "Physical Challenges in Reliable Graphics Hardware Design." PhD dissertation, Univ. of Virginia School of Engineering and Applied Science, Aug. 2007. Available in pdf.
W. Huang, K. Sankaranarayanan, R. J. Ribando, M. R. Stan, and K. Skadron. “An Improved Block-Based Thermal Model in HotSpot-4.0 with Granularity Considerations.” In Proceedings of the Workshop on Duplicating, Deconstructing, and Debunking, in conjunction with the 34th International Symposium on Computer Architecture (ISCA), June 2007. (pdf)
E. Humenay, D. Tarjan, and K. Skadron. "Impact of Process Variations on Multicore Performance Symmetry." In Proceedings of the 2007 Conference on Design, Automation and Test in Europe, pp. 1653-58, Apr. 2007. (pdf)
W. Huang, K. Sankaranarayanan, R. J. Ribando, M. R. Stan, and K. Skadron. “An Improved Block-Based Thermal Model in HotSpot 4.0 with Granularity Considerations.” Tech Report CS-2007-07, Univ. of Virginia Dept. of Computer Science, Feb. 2007. (pdf)
Z. Lu, W. Huang, M. Stan, K. Skadron, and J. Lach. “Interconnect Lifetime Prediction for Reliability-Aware Systems.” IEEE Transactions on VLSI Systems, 15(2):159-72, Feb. 2007. (pdf)
W. Huang. "HotSpot—A Chip and Package Compact Thermal Modeling Methodology for VLSI Design." PhD dissertation, Univ. of Virginia School of Engineering and Applied Science, Jan. 2007. Available in pdf
Z. Lu. "Runtime Management Techniques for Power- and Temperature-aware Computing." PhD dissertation, Univ. of Virginia School of Engineering and Applied Science, Jan. 2007. Available in pdf.
E. Humenay. "Impact of Systematic Variations on Performance Symmetry in Multi-core Chips." MCS project, Univ. of Virginia School of Engineering and Applied Science, Jan. 2007.
S. W. Chung and K. Skadron. "A Novel Software Solution for Localized Thermal Problems" In Proceedings of the 4th International Symposium on Parallel and Distributed Processing and Applications (ISPA), Springer-Verlag LNCS, pp. 63-74, Dec. 2006. (pdf)
Y. Li, K. Skadron, B. C. Lee, and D. Brooks. “Quantifying Latency and Throughput Compromises in CMP Designs.” Tech Report CS-2006-26, Univ. of Virginia Dept. of Computer Science, Dec. 2006. (pdf)
Z. Lu, W. Huang, M. R. Stan, K. Skadron, and J. Lach. "Interconnect Lifetime Prediction with Temporal and Spatial Temperature Gradients for Reliability-Aware Design and Runtime Management: Modeling and Applications." Tech Report CS-2006-23, Univ. of Virginia Dept. of Computer Science, Oct. 2006. (pdf)
Y. Li. "Physically Constrained Chip Multiprocessor Architecture." PhD dissertation, Univ. of Virginia School of Engineering and Applied Science, Aug. 2006. Available in pdf
E. Humenay, D. Tarjan, and K. Skadron. “Impact of Parameter Variations on Multi-Core Chips.” In Proceedings of the 2006 Workshop on Architectural Support for Gigascale Integration, in conjunction with the 33rd International Symposium on Computer Architecture (ISCA), June 2006. (pdf)
W. Huang, S. Ghosh, S. Velusamy, K. Sankaranarayanan, K. Skadron, and M. R. Stan. “HotSpot: A Compact Thermal Modeling Methodology for Early-Stage VLSI Design.” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 14(5):501-513, May 2006. (pdf) Google Scholar Classic Paper in in Computer Hardware Design for 2006 (3rd most cited paper).
S. W. Chung and K. Skadron. “Using on-Chip Event Counters for High-Resolution, Real-Time Temperature Measurements.” In Proceedings of the IEEE/ASME Tenth Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITHERM), June 2006. (pdf)
Y. Li, B. Lee, D. Brooks, Z. Hu, and K. Skadron. “Impact of Thermal Constraints on Multi-Core Architectures.” In Proceedings of the IEEE/ASME Tenth Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITHERM), June 2006. (pdf).
K. Skadron. “Thermal Challenges in Architecting Multi-Core Chips,” position paper for a panel on “Challenges in Chip/Processor Level Thermal Engineering,” organized by M. Asheghi and D. Agonafer. In Proceedings of the IEEE/ASME Tenth Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITHERM), June 2006.
S. W. Chung and K. Skadron. "A Novel Software Solution for Localized Thermal Problems." Tech Report CS-2006-10, Univ. of Virginia Dept. of Computer Science, Apr. 2006. (pdf)
E. E. Otto, “Temperature-Aware Operating System Scheduling to Manage the Impact of Thermal Throttling.” Senior thesis, Univ. of Virginia School of Engineering and Applied Science, Apr. 2006. (pdf)
Y. Li, B. C. Lee, D. Brooks, Z. Hu, and K. Skadron. "CMP Design Space Exploration Subject to Physical Constraints." In Proceedings of the Twelfth IEEE International Symposium on High Performance Computer Architecture (HPCA), pp. 15-26, Feb. 2006. (pdf)
Z. Lu, J. Lach, M. R. Stan, and K. Skadron. “Improved Thermal Management with Reliability Banking.” IEEE Micro, 25(6):40-49, Nov./Dec. 2005 special issue on Reliability-Aware Microarchitectures. (pdf)
W. Huang, S. Ghosh, K. Sankaranarayanan, K. Skadron, and M. R. Stan. “Parameterized Physical Compact Thermal Modeling.” IEEE Transactions on Component Packaging and Manufacturing Technology, 28(4):615-22, Dec. 2005. (pdf)
K.-J. Lee, K. Skadron, and W. Huang. “Analytical Model for Sensor Placement on Microprocessors.” In Proceedings of the IEEE International Conference on Computer Design (ICCD), Oct. 2005, pp. 24-27. (pdf)
S. Velusamy, W. Huang, J. Lach, M. R. Stan, and K. Skadron. “Monitoring Temperature in FPGA based SoCs.” In Proceedings of the IEEE International Conference on Computer Design (ICCD), Oct. 2005, pp. 634-37. (pdf)
E. Humenay, W. Huang, M. R. Stan, and K. Skadron. “Toward an Architectural Treatment of Parameter Variations.” Tech Report CS-2005-16, Univ. of Virginia Dept. of Computer Science, Sept. 2005. (pdf)
K. Sankaranarayanan, S. Velusamy, M.R. Stan, and K. Skadron. "A Case for Thermal-Aware Floorplanning at the Microarchitectural Level." The Journal of Instruction-Level Parallelism, vol. 7, Oct. 2005, http://www.jilp.org/vol7/. (pdf)
Y. Li, M. Hempstead, P. Mauro, D. Brooks, Z. Hu, and K. Skadron. “Power and Thermal Effects of SRAM vs. LatchMux Design.” In Proceedings of the ACM/IEEE 2005 International Symposium on Low-Power Electronics Design (ISLPED), pp. 173-178, Aug. 2005. (pdf)
W. Huang, E. Humenay, K. Skadron, and M. R. Stan. “The Need for a Full Chip and Package Thermal Model for Thermally Optimized IC Designs.” In Proceedings of the ACM/IEEE 2005 International Symposium on Low-Power Electronics Design (ISLPED), pp. 245-50, Aug. 2005. (pdf)
Z. Lu, J. Lach, M. Stan, and K. Skadron. “Temperature-Aware Modeling and Banking of IC Lifetime Reliability.” Tech Report CS-2005-10, Univ. of Virginia Dept. of Computer Science, June 2005.
K. Sankaranarayanan, S. Velusamy, and K. Skadron. “Microarchitectural Floorplanning for Thermal Management: A Technical Report.” Tech Report CS-2005-08, Univ. of Virginia Dept. of Computer Science, May 2005.
K.-J. Lee, “Microarchitectural Temperature Modeling Using Performance Counters.” Senior thesis, Univ. of Virginia School of Engineering and Applied Science, Apr. 2005. (pdf)
K.-J. Lee and K. Skadron. “Using Performance Counters for Runtime Temperature Sensing in High-Performance Processors.” In Proceedings of the Workshop on High-Performance, Power-Aware Computing (HP-PAC), in conjunction with the 2005 International Parallel and Distributed Processing Symposium, Apr. 2005. Available in pdf [Presentation slides pdf]
P. Dadvar, “Security Threats of Power and Thermal Control Intefaces.” Senior thesis, Univ. of Virginia School of Engineering and Applied Science, Apr. 2005. (pdf)
P. Dadvar and K. Skadron. “Potential Thermal Security Risks.” In Proceedings of the IEEE Semiconductor Thermal Measurement, Modeling, and Management Symposium (Semi-Therm 21), pp. 229-34, Mar. 2005. Available in pdf
J. W. Sheaffer, K. Skadron, and D. P. Luebke. “Studying Thermal Management for Graphics-Processor Architectures.” In Proceedings of the 2005 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), Mar. 2005. (pdf)
Y. Li, D. Brooks, Z. Lu, and K. Skadron. “Power and Thermal Effects of Different Clock Gating Schemes in General Purpose Processors.” Poster and associated paper at the IBM Austin Conference on Energy-Efficient Design (ACEED), Mar. 2005.
S. Velusamy, W. Huang, J. Lach, M. Stan, and K. Skadron. “Experiences using FPGAs for Temperature-Aware Microarchitecture Research.” In the 2005 Workshop on Architecture Research using FPGA Platforms (WARFP), in conjunction with the 11th IEEE International Symposium on High Performance Computer Architecture, Feb. 2005. Available in pdf
Y. Li, K. Skadron, Z. Hu, and D. Brooks. “Performance, Energy, and Thermal Considerations for SMT and CMP Architectures.” Proceedings of the Eleventh IEEE International Symposium on High Performance Computer Architecture (HPCA), Feb. 2005. Available in pdf
Y. Li, K. Skadron, D. Brooks, M. Hempstead, P. Mauro, and Z. Hu. “Power and Thermal Effects of SRAM vs. Latch-Mux Design Styles and Clock Gating Choices.” Tech Report CS-2005-01, Univ. of Virginia Dept. of Computer Science, Feb. 2005.
S. Velusamy, W. Huang, J. Lach, and K. Skadron. “Monitoring Temperature in FPGA based SoCs.” Tech Report CS-2004-39, Univ. of Virginia Dept. of Computer Science, Dec. 2004.
Y. Li, Z. Hu, D. Brooks, and K. Skadron. “Performance, Energy and Thermal Considerations for SMT and CMP Architectures: Extended Discussion and Results.” Tech Report CS-2004-32, Univ. of Virginia Dept. of Computer Science, Nov. 2004. (Extended version of HPCA-11 paper.)
Z. Lu, W. Huang, J. C. Lach, M. R. Stan, and K. Skadron. “Interconnect Lifetime Prediction under Dynamic Stress for Reliability-Aware Design.” In Proceedings of the IEEE/ACM International Conference on Computer Aided Design (ICCAD), pp. 327-34, Nov. 2004. Available in pdf
Y. Li, K. Skadron, Z. Hu, and D. Brooks. “Evaluating the Thermal Efficiency of SMT and CMP Architectures.” In the IBM Watson Conference on Interaction between Architecture, Circuits, and Compilers, external track, Oct. 2004. (Also published as IBM TJ Watson Research Report RC23281, July 2004.) Available in pdf
W. Huang, M. R. Stan, and K. Skadron. “Physically-Based Compact Thermal Modeling—Achieving Parameterization and Boundary Condition Independence.” In Proceedings of the 9th International Workshop on Thermal Investigations of ICs (THERMINIC), Sept. 2004, pp. 287-92. Available in pdf
J. W. Sheaffer, D. P. Luebke, and K. Skadron. “Temperature-Aware GPU Design.” SIGGRAPH 2004 poster session, Aug. 2004. (One of 5 semi-finalists for the SIGGRAPH Student Research Competition out of 53 SRC entries and 118 total posters accepted.) Available in pdf [associated video, AVI]
W. Huang, S. Ghosh, K. Sankaranarayanan, K. Skadron, and M. R. Stan. “Compact Thermal Modeling for Temperature-Aware Design.” Tech Report CS-2004-13, Univ. of Virginia Dept. of Computer Science, Apr. 2004. (Extended version of DAC 2004 paper.)
W. Huang, S. Ghosh, K. Sankaranarayanan, K. Skadron, and M. R. Stan. “Compact Thermal Modeling for Temperature-Aware Design.” In Proceedings of the 41st ACM/IEEE Design Automation Conference (DAC), pp. 878-883, June 2004. Available in pdf
K. Skadron. “The Importance of Computer Architecture in Microprocessor Thermal Design,” position paper for a panel on “Challenges in Chip/Processor Level Thermal Engineering,” organized by M. Asheghi and D. Agonafer. In Proceedings of the IEEE/ASME Ninth Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITHERM), June 2004.
S. S. Kim. "Characterizing Thermal Behavior of Pentium-IV with Hyperthreading." Senior thesis, Univ. of Virginia School of Engineering and Applied Science, Apr. 2004. Available in pdf
E. Wirth, "Thermal Management in Embedded Systems." Senior thesis, Univ. of Virginia School of Engineering and Applied Science, Apr. 2004. Available in pdf
K. Skadron, K. Sankaranarayanan, S. Velusamy, D. Tarjan, M.R. Stan, and W. Huang. “Temperature-Aware Microarchitecture: Modeling and Implementation.” ACM Transactions on Architecture and Code Optimization, 1(1):94-125, Mar. 2004. Available in pdf.
K. Skadron, M.R. Stan, W. Huang, K. Sankaranarayanan, Z. Lu, and J. Lach. “The Need for a Computer-Architecture Approach to Thermal Management in Computer Systems.” In Proceedings of the 5th IEEE International Conference on Thermal, Mechanical and Thermo-Mechanical Simulation and Experiments in Micro-electronics and Micro-systems (EuroSimE), pp. 415-22, May 2004. (Keynote presentation within session.) Available in pdf
K. Skadron. “Hybrid Architectural Dynamic Thermal Management.” In Proceedings of the 2004 Design, Automation and Test in Europe (DATE) Conference, pp. 10-15, Feb. 2004. Available in pdf
W. Huang, Z. Lu, S. Ghosh, M. Stan, J. Lach, and K. Skadron. “The Importance of Temporal and Spatial Temperature Gradients in IC Reliability Analysis.” Tech Report CS-2004-07, Univ. of Virginia Dept. of Computer Science, Jan. 2004.
K. Skadron, M.R. Stan, W. Huang, S. Velusamy, K. Sankaranarayanan, and D. Tarjan. “Temperature-Aware Computer Systems: Opportunities and Challenges.” IEEE Micro, 23(6):52-61, Nov-Dec. 2003. (Special issue on “Top Picks from Microarchitecture Conferences” for 2003) Available in pdf.
Z. Lu, M. Stan, J. Lach, and K. Skadron. “Interconnect Lifetime Prediction for Temperature-Aware Design.” Tech Report CS-2003-21, Univ. of Virginia Dept. of Computer Science, Nov. 2003
K. Skadron, M. R. Stan, W. Huang, S. Velusamy, K. Sankaranarayanan, and D. Tarjan. “Temperature-Aware Microarchitecture.” In Proceedings of the 30th International Symposium on Computer Architecture, pp. 2-13, June 2003. Available in postscript or pdf (Abstract) [software home page] (Extended version appears as TR CS-2003-08.) (Best student paper!)
K. Skadron, M. R. Stan, W. Huang, S. Velusamy, K. Sankaranarayanan, and D. Tarjan. “Temperature-Aware Microarchitecture: Extended Discussion and Results.” University of Virginia Dept. of Computer Science Technical Report CS-2003-08, Apr. 2003. Available in postscript or pdf (Abstract) [software home page]
M. R. Stan, K. Skadron, M. Barcella, W. Huang, K. Sankaranarayanan, and S. Velusamy. “HotSpot: A Dynamic Compact Thermal Model at the Processor-Architecture Level.” Microelectronics Journal: Circuits and Systems, Elsevier, 34(12):1153-65, Dec. 2003. Available in pdf (Abstract)
K. Skadron et al. “HotSpot: Techniques for Modeling Thermal Effects at the Processor-Architecture Level”. In Proceedings of the 2002 International Workshop on THERMal Investigations of ICs and Systems (THERMINIC), pp. 169-72, Oct. 2002. Available in postscript or pdf (Abstract)
M. Barcella, W. Huang, M. Stan, and K. Skadron. “Architecture-Level Compact Thermal R-C Modeling.” Tech Report CS-2002-20, Univ. of Virginia Dept. of Computer Science, July 2002. Available in postscript (Abstract)
K. Skadron, T. Abdelzaher, and M. Stan. "Control-Theoretic Techniques and Thermal-RC Modeling for Accurate and Localized Dynamic Thermal Management." In Proceedings of the Eighth International Symposium on High-Performance Computer Architecture, pp. 17-28, Feb. 2002. (Extended version appears as TR CS-2001-27.) Available in postscript or pdf (Abstract) Erratum
K. Skadron, T. Abdelzaher, and M.R. Stan. “Control-Theoretic Techniques and Thermal-RC Modeling for Accurate and Localized Dynamic Thermal Management.” Tech Report CS-2001-27, Univ. of Virginia Dept. of Computer Science, Nov. 2001. (Extended version of HPCA-8 paper.) Available in postscript or pdf (Abstract) Erratum

Power

VoltSpot software - now version 2!
HotLeakage software home page
DelayDVS and ClusterControlWare - software for power management in multi-tier servers
R. Zhang, B. H. Meyer, K. Wang, M. R. Stan, and K. Skadron. “Tolerating the Consequences of Multiple EM-induced C4 Bump Failures.” IEEE Transactions on VLSI Systems (TVLSI), 24(6):2335-44, June 2016. DOI 10.1109/TVLSI.2015.2501353.
R. Zhang, K. Mazumder, B. H. Meyer, K. Wang, K. Skadron, and M. R. Stan. “Transient Voltage Noise in Charge-Recycled Power Delivery Networks for Many-Layer 3D-IC.” In Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), July 2015. (pdf)
L. Wang, A. Vega, A. Buyuktosonoglu, K. Skadron, and P. Bose. “Power-Efficient Embedded Processing with Resilience.” In Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), July 2015. (pdf)
R. Zhang, K. Mazumder, B. H. Meyer, K. Wang, K. Skadron, and M. R. Stan. “A Cross-Layer Design Exploration of Charge-Recycled Power Delivery in Many-Layer 3D-IC.” In Proceedings of the ACM/IEEE International Design Automation Conference (DAC), June 2015. (pdf)
R. Zhang. "Pre-RTL On-Chip Power Delivery Modeling and Analysis." PhD dissertation, Univ. of Virginia School of Engineering and Applied Science, May 2015. (pdf)
R. Zhang, K. Wang, B. H. Meyer, M. R. Stan, and K. Skadron. "Architecture Implications of Pads as a Scarce Resource." In Proceedings of the ACM/IEEE International Symposium on Computer Architecture, June 2014. (pdf)
R. Zhang, K. Wang, B. H. Meyer, M. R. Stan, and K. Skadron. "Architectural Implications of Pads as a Scarce Resource: Extended Results." Tech. Report CS-2014-01, Univ. of Virginia Dept. of Computer Science, May 2014. (pdf)
K. Wang, R. Zhang, B. H. Meyer, M. R. Stan, and K. Skadron. "Managing C4 Placement for Transient Voltage Noise Minimization." In Proceedings of the ACM/IEEE Conference on Design Automation (DAC), June 2014 (please download from this listing).
K. Wang, R. Zhang, B. H. Meyer, K. Skadron, and M. R. Stan. "Walking Pads: Fast Power-Supply Pad-Placement Optimization." In Proceedings of the ACM/IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), Jan. 2014. Best paper candidate. (preprint pdf)
W. Huang, K. Rajamani, M. R. Stan, and K. Skadron. "Scaling with Design Constraints – Predicting the Future of Big Chips." IEEE Micro special issue on Big Chips, 31(4):16-29, July/Aug. 2011, DOI 10.1109/MM.2011.42.
R. Zhang, B. H. Meyer, W. Huang, K. Skadron, and M. R. Stan. "Some Limits of Power Delivery in the Multicore Era." In Proceedings of the Workshop on Energy Efficient Design (WEED), in conjunction with ISCA, June 2012. (pdf)
M. Gebhart, D. R. Johnson, D. Tarjan, S. W. Keckler, W. J. Dally, E. Lindholm, and K. Skadron. " A Hierarchical Thread Scheduler and Register File for Energy-efficient Throughput Processors." ACM Transactions on Computer Systems (TOCS), 30(2), 38 pages, Apr. 2012. DOI 10.1145/2166879.2166882. (preprint pdf)
M. Gebhart, D. R. Johnson, D. Tarjan, S. W. Keckler, W. J. Dally, E. Lindholm, and K. Skadron. "Energy-efficient Mechanisms for Managing Thread Context in Throughput Processors." In Proceedings of the ACM/IEEE International Symposium on Computer Architecture (ISCA), June 2011. (pdf)
S. Che, M. Boyer, J. Meng, D. Tarjan, J. W. Sheaffer, S.-H. Lee, and K. Skadron. “Rodinia: A Benchmark Suite for Heterogeneous Computing.” In Proceedings of the IEEE International Symposium on Workload Characterization (IISWC), pp. 44-54, Oct. 2009. (pdf)
J. Meng and K. Skadron “Avoiding Cache Thrashing due to Private Data Placement in Last-Level Cache for Manycore Scaling.” In Proceedings of the IEEE International Conference on Computer Design (ICCD), pp. 282-88, Oct. 2009. (pdf)
T. Horvath and K. Skadron. "Multi-mode Energy Management for Multi-tier Server Clusters." In Proceedings of the ACM/IEEE/IFIP International Conference on Parallel Architectures and Compilation Techniques (PACT), pp. 270-79, Oct. 2008. (pdf | DelayDVS and ClusterControlWare software)
T. Horvath. "Energy Management in Real-Time Multi-Tier Internet Services." PhD dissertation, Univ. of Virginia School of Engineering and Applied Science, May 2008. Available in pdf.
S. W. Chung and K. Skadron. “On-Demand Solution to Minimize I-Cache Leakage Energy with Maintaining Performance.” IEEE Transactions on Computers, 57(1):7-24, Jan. 2008, DOI 10.1109/TC.2007.70770. (pdf)
K. Skadron, P. Bose, K. Ghose, R. Sendag, J. J. Yi, and D. Chiou. "Low-Power Design and Temperature Management." IEEE Micro, 27(6):46-57, Nov.-Dec. 2007. DOI 10.1109/MM.2007.104. (pdf)
J. W. Sheaffer. "Physical Challenges in Reliable Graphics Hardware Design." PhD dissertation, Univ. of Virginia School of Engineering and Applied Science, Aug. 2007. Available in pdf.
T. Horvath, T. Abdelzaher, and K. Skadron. “Dynamic Voltage Scaling in Multi-tier Web Servers with End-to-end Delay Control.” IEEE Transactions on Computers, 56(4):444-58, Apr. 2007. (pdf)
T. Horvath, K. Skadron, and T. Abdelzaher. "Enhancing Energy Efficiency in Multi-tier Web Server Clusters via Prioritization." In Proceedings of the 2007 NSF Next Generation Software Workshop, in conjunction with the IEEE International Parallel and Distributed Processing Symposium, Mar. 2007. (pdf)
E. Humenay, D. Tarjan, and K. Skadron. "Impact of Process Variations on Multicore Performance Symmetry." In Proceedings of the 2007 Conference on Design, Automation and Test in Europe, pp. 1653-58, Apr. 2007. (pdf)
Z. Lu. "Runtime Management Techniques for Power- and Temperature-aware Computing." PhD dissertation, Univ. of Virginia School of Engineering and Applied Science, Jan. 2007. Available in pdf.
E. Humenay. "Impact of Systematic Variations on Performance Symmetry in Multi-core Chips." MCS project, Univ. of Virginia School of Engineering and Applied Science, Jan. 2007.
Y. Li, K. Skadron, B. C. Lee, and D. Brooks. “Quantifying Latency and Throughput Compromises in CMP Designs.” Tech Report CS-2006-26, Univ. of Virginia Dept. of Computer Science, Dec. 2006. (pdf)
Z. Lu, J. Lach, K. Skadron, and M. R. Stan. “Design and Implementation of an Energy Efficient Multimedia Playback System.” In Proceedings of the 40th Asilomar Conference on Signals, Systems and Computers, Oct. 2006. (pdf)
M. Co, D. A. B. Weikle, and K. Skadron. "Evaluating Trace Cache Energy Efficiency." ACM Transactions on Architecture and Code Optimization (TACO), 3(4):450-76, Dec. 2006. (Abstract | pdf)
S. W. Chung and K. Skadron. "Using Branch Prediction Information for Near-Optimal I-Cache Leakage Reduction." In Proceedings of the 11th Asia-Pacific Systems Architecture Conference (ACSAC), Sept. 2006, pp. 24-37. (pdf)
Y. Li. "Physically Constrained Chip Multiprocessor Architecture." PhD dissertation, Univ. of Virginia School of Engineering and Applied Science, Aug. 2006. Available in pdf
E. Humenay, D. Tarjan, and K. Skadron. “Impact of Parameter Variations on Multi-Core Chips.” In Proceedings of the 2006 Workshop on Architectural Support for Gigascale Integration, in conjunction with the 33rd International Symposium on Computer Architecture (ISCA), June 2006. (pdf)
S .W. Chung and K. Skadron. “Using Branch Prediction Information for Near-Optimal I-Cache Leakage Reduction.” Tech Report CS-2006-03, Univ. of Virginia Dept. of Computer Science, Mar. 2006. (pdf)
Z. Lu, Y. Zhang, M. R. Stan, J. Lach, and K. Skadron. “Procrastinating Voltage Scheduling with Discrete Frequency Sets.” In Proceedings of the ACM/IEEE/EDAA/EDAC 2006 Design, Automation and Test in Europe Conference (DATE), pp. 456-61, Mar. 2006. (pdf)
Y. Li, B. C. Lee, D. Brooks, Z. Hu, and K. Skadron. "CMP Design Space Exploration Subject to Physical Constraints." In Proceedings of the Twelfth IEEE International Symposium on High Performance Computer Architecture (HPCA), pp. 15-26, Feb. 2006. (pdf)
V. Narayanan and K. Skadron. "Architectural/System Design and Optimization," in "CAD Algorithms, Methods and Tools For Low-Power Circuits and Systems," E. Macii ed. IEEE Council on Electronic Design Automation (C-EDA) Technology Survey, Jan. 2006. (IEEE Xplore link)
Y. Li, M. Hempstead, P. Mauro, D. Brooks, Z. Hu, and K. Skadron. “Power and Thermal Effects of SRAM vs. LatchMux Design.” In Proceedings of the ACM/IEEE 2005 International Symposium on Low-Power Electronics Design (ISLPED), pp. 173-178, Aug. 2005. (pdf)
Y. Zhang, Z. Lu, M. R. Stan, J. Lach, and K. Skadron. “Optimal Procrastinating Voltage Scheduling for Hard Real-Time Systems.” In Proceedings of the ACM/IEEE 42nd Design Automation Conference (DAC), pp. 905-08, June 2005. (pdf)
D. McWhorter, “Power Consumption Characterization of a Graphics Processing Unit.” Senior thesis, Univ. of Virginia School of Engineering and Applied Science, Apr. 2005. (pdf)
Y. Li, D. Brooks, Z. Lu, and K. Skadron. “Power and Thermal Effects of Different Clock Gating Schemes in General Purpose Processors.” Poster and associated paper at the IBM Austin Conference on Energy-Efficient Design (ACEED), Mar. 2005.
Y. Li, K. Skadron, Z. Hu, and D. Brooks. “Performance, Energy, and Thermal Considerations for SMT and CMP Architectures.” Proceedings of the Eleventh IEEE International Symposium on High Performance Computer Architecture (HPCA), Feb. 2005. Available in pdf
Y. Li, K. Skadron, D. Brooks, M. Hempstead, P. Mauro, and Z. Hu. “Power and Thermal Effects of SRAM vs. Latch-Mux Design Styles and Clock Gating Choices.” Tech Report CS-2005-01, Univ. of Virginia Dept. of Computer Science, Feb. 2005.
T. Horvath, T. Abdelzaher, and K. Skadron. “Dynamic Voltage Scaling in Multi-tier Web Servers with End-to-end Delay Control.” Tech Report CS-2004-34, Univ. of Virginia Dept. of Computer Science, Nov. 2004.
J. C. Lach, J. M. Brandon, and K. Skadron. “A General Post-Processing Approach to Leakage Current Reduction in SRAM-based FPGAs.” In Proceedings of the IEEE International Conference on Computer Design (ICCD), pp. 144-50, Oct. 2004. Available in pdf
M. Co and K. Skadron. "Evaluating Trace Cache Energy-Efficiency." Tech Report CS-2004-31, Univ. of Virginia Dept. of Computer Science, Oct. 2004.
K. Sankaranarayanan and K. Skadron. “Profile-Based Adaptation for Cache Decay”. ACM Transactions on Architecture and Code Optimization, 1(3):305-322, Sep. 2004. Available in pdf.
Y. Li, D. Brooks, Z. Hu, K. Skadron, and P. Bose. “Understanding the Energy Efficiency of Simultaneous Multithreading.” In Proceedings of the ACM/IEEE 2004 International Symposium on Low-Power Electronics Design (ISLPED), pp. 44-49, Aug. 2004. Available in pdf
J. W. Sheaffer, D. P. Luebke, and K. Skadron. “A Flexible Simulation Framework for Graphics Architectures.” In Proceedings of Eurographics/ACM Graphics Hardware 2004 (GH), pp. 85-94, Aug. 2004. Available in pdf [associated video, AVI]
P. Juang, K. Skadron, M. Martonosi, Z. Hu, D. W. Clark, P. W. Diodato, and S. Kaxiras. “Implementing Branch Predictor Decay Using Quasi-Static Memory Cells.” ACM Transactions on Architecture and Code Optimization, 1(2):180-219, June 2004. Available in pdf.
D. Parikh, K. Skadron, Y. Zhang, and M. Stan. "Power-Aware Branch Prediction, Characterization and Design." IEEE Transactions on Computers, 53(2):168-86, Feb. 2004. Available in pdf (Abstract)
Y. Li, D. Parikh, Y. Zhang, K. Sankaranarayanan, M. R. Stan, and K. Skadron. “State-Preserving vs. Non-State-Preserving Leakage Control in Caches.” In Proceedings of the 2004 Design, Automation and Test in Europe (DATE) Conference, pp. 22-27, Feb. 2004. Available in pdf [HotLeakage software home page]
V. Sharma, A. Thomas, T. Abdelzaher, Z. Lu, and K. Skadron. “Power-Aware QoS Management on Web Servers.” In Proceedings of the 24th International Real-Time Systems Symposium, pp. 63-72, Dec. 2003. Available in pdf (Best student paper!)
M. R. Stan and K. Skadron. “Power Aware Computing,” guest editor’s introduction. IEEE Computer, 36(12), Dec. 2003. Available in pdf
M. Co and K. Skadron. "Evaluating the Energy Efficiency of Trace Caches." Tech Report CS-2003-19, Univ. of Virginia Dept. of Computer Science, Oct. 2003.
Y. Li, K. Skadron, and M.R. Stan. "New Findings on Using Queue Occupancy to Integrate Runtime Power-Saving Techniques Across the Pipeline." Tech Report CS-2003-15, Univ. of Virginia Dept. of Computer Science, July 2003.
Z. Lu, J. Lach, M.R. Stan, and K. Skadron. "Reducing Multimedia Decode Power using Feedback Control." In Proceedings of the 2003 International Conference on Computer Design, pp. 489-96, Oct. 2003.Available in pdf (Abstract)
K. Sankaranarayanan. "Profile-Based Adaptation for Cache Decay." MCS project, Univ. of Virginia School of Engineering and Applied Science, Aug. 2003.
D. Parikh, Y. Zhang, K. Sankaranarayanan, K. Skadron, and M. Stan. "Comparison of State-Preserving vs. Non-State-Preserving Leakage Control in Caches." In Proceedings of the Second Annual Workshop on Duplicating, Deconstructing, and Debunking in conjunction with ISCA-30, June 2003. Available in postscript or pdf (Abstract) [HotLeakage software home page]
A. Thomas, "A Measurement Platform for DVS Algorithm Development and Analysis." Senior thesis, Univ. of Virginia School of Engineering and Applied Science, Apr. 2003. Available in pdf
Y. Zhang, D. Parikh, K. Sankaranarayanan, K. Skadron, and M. Stan. "HotLeakage: A Temperature-Aware Model of Subthreshold and Gate Leakage for Architects." Tech Report CS-2003-05, Univ. of Virginia Dept. of Computer Science, Mar. 2003. Available in postscript or pdf (Abstract) [software home page]
D. Parikh. "Power Aware Branch Prediction: Characterization and Design." MCS project, Univ. of Virginia School of Engineering and Applied Science, Jan. 2003. Available in pdf
Z. Lu, J. Hein, M. Humphrey, M. Stan, J. Lach, and K. Skadron. “Control-Theoretic Dynamic Frequency and Voltage Scaling for Multimedia Workloads.” In Proceedings of the 2002 International Conference on Compilers, Architectures, and Synthesis for Embedded Systems, pp. 156-163, Oct. 2002. Available in postscript or pdf (Abstract)
P. Juang, P. Diodato, S. Kaxiras, K. Skadron, Z. Hu, M. Martonosi, and D.W. Clark. "Implementing Decay Techniques using 4T Quasi-Static Memory Cells." Computer Architecture Letters, Volume 1, Sept. 2002. Available in postscript or pdf (Abstract)
Z. Hu, P. Juang, K. Skadron, D. Clark, and M. Martonosi. “Applying Decay Strategies to Branch Predictors for Leakage Energy Savings.” In Proceedings of the 2002 International Conference on Computer Design, pp. 442-45, Sept. 2002. Available in pdf (Abstract)
Z. Hu, P. Juang, S. Kaxiras, P. Diodato, K. Skadron, D.W. Clark, and M. Martonosi. “Managing Leakage for Transient Data : Decay and Quasi-Static Memory Cells.” In Proceedings of the 2002 International Symposium on Low-Power Electronics and Design, pp. 52-55, Aug. 2002. Available in pdf (Abstract)
Y. Zhang, J. Lach, K. Skadron, and M.R. Stan. “Odd/Even Bus Invert with Two-Phase Transfer for Buses with Coupling.” In Proceedings of the 2002 International Symposium on Low-Power Electronics and Design, pp. 80-83, Aug. 2002. Available in pdf
Z. Lu, J. Hein, M. Humphrey, M. Stan, J. Lach, and K. Skadron. “Control-Theoretic Dynamic Frequency and Voltage Scaling.” In Proceedings of the 2002 Workshop on Self-Healing, Adaptive, and Self-Managed Systems, held in conjunction with ICS 2002, June 2002. (best student paper!) Available in postscript or pdf (Abstract)
S. Velusamy, K. Sankaranarayanan, D. Parikh, T. Abdelzaher, and K. Skadron. “Adaptive Cache Decay using Formal Feedback Control.” In Proceedings of the Workshop on Memory Performance Issues, held in conjunction with ISCA-29, May 2002. Available in postscript or pdf (Abstract)
A. Spanberger, “Designing a Dynamically Reconfigurable Cache for High Performance and Low Power.” Senior thesis, Univ. of Virginia School of Engineering and Applied Science, Apr. 2002 (finalist in the 2002 SEAS Undergraduate Research and Design Symposium). Available in pdf
D. Parikh, K. Skadron, Y. Zhang, M. Barcella, and M. Stan. "Power Issues Related to Branch Prediction." In Proceedings of the Eighth International Symposium on High-Performance Computer Architecture, pp. 233-44, Feb. 2002. (Extended version appears as TR CS-2001-25.) Available in postscript or pdf (Abstract)
D. Parikh, K. Skadron, Y. Zhang, M. Barcella, and M. Stan. “Power Issues Related to Branch Prediction.” Tech Report CS-2001-25, Univ. of Virginia Dept. of Computer Science, Nov. 2001. (Extended version of HPCA-8 paper.) Available in pdf (Abstract)
Z. Hu, P. Juang, K.Skadron, M. Martonosi, and D. W. Clark. “Applying Decay Strategies to Branch Predictors for Leakage Energy Savings.” Tech Report CS-2001-24, Univ. of Virginia Dept. of Computer Science, Oct. 2001. Available in pdf (Abstract)

Reliability

J. P. Wadden and K. Skadron. “Advances in GPU Reliability Research.” In Advances in GPU Research and Practice, edited by H. Sarbazi-Azad. Elsevier, 2016.
E. Cheng, S. Mirkhani, L. G. Szafaryn, C.-Y. Cher, H. Cho, K. Skadron, M. R. Stan, K. Lilja, J. A. Abraham, P. Bose, and S. Mitra. “CLEAR: Cross-Layer Exploration for Architecting Resilience - Combining Hardware and Software Techniques to Tolerate Soft Errors in Processor Cores.” In Proceedings of the ACM/IEEE Design Automation Conference (DAC), June 2016. (pdf)
L. Wang, A. Vega, A. Buyuktosonoglu, K. Skadron, and P. Bose. “Power-Efficient Embedded Processing with Resilience.” In Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), July 2015. (pdf)
L. Szafaryn. "Understanding and Optimizing Heterogeneous Soft-Error Protection." PhD dissertation, Univ. of Virginia School of Engineering and Applied Science, May 2015. (pdf)
Y. Li and K. Skadron. "TMR: A Solution for Hardware Security Designs." Tech. Report CS-2015-02, Univ. of Virginia Dept. of Computer Science, Apr. 2015. (pdf)
J. Wadden, A. Lyashevsky, S. Gurumurthi, V. Sridharan, and K. Skadron. "Real-World Design and Evaluation of Compiler-Managed GPU Redundant Multithreading." In Proceedings of the ACM/IEEE International Symposium on Computer Architecture, June 2014. (pdf)
K. Wang, R. Zhang, B. H. Meyer, M. R. Stan, and K. Skadron. "Managing C4 Placement for Transient Voltage Noise Minimization." In Proceedings of the ACM/IEEE Conference on Design Automation (DAC), June 2014. (paper)
L. Wang, J. A. Rivers, M. S. Gupta, A. J. Vega, A. Buyuktosunoglu, P. Bose, and K. Skadron. "Resilience and Real-Time Constrained Energy Optimization in Embedded Processor Systems." In Proceedings of the IEEE Workshop on Silicon Errors in Logic - System Effects, April 2014. (pdf)
K. Wang, R. Zhang, B. H. Meyer, K. Skadron, and M. R. Stan. "Walking Pads: Fast Power-Supply Pad-Placement Optimization." In Proceedings of the ACM/IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), Jan. 2014. Best paper candidate. (preprint pdf)
L. Szafaryn, B. H. Meyer, and K. Skadron. "Evaluating the Overheads of Soft Error Protection Mechanisms in the Context of Multi-bit Errors at the Scope of a Processor Core." IEEE Micro special issue on Reliability Aware Design, 33(4):56-65, July-Aug. 2013. DOI 10.1109/MM.2013.68. (preprint pdf)
B. Meyer, B. Calhoun, J. Lach, and K. Skadron. "Cost-effective Safety and Fault Localization using Distributed Temporal Redundancy." In Proceedings of the ACM/IEEE International Conference on Compilers, Architectures, and Synthesis for Embedded Systems (CASES), Oct. 2011. (pdf)
B. Meyer, N. George, B. Calhoun, J. Lach, and K. Skadron. "Reducing the Cost of Redundant Execution in Safety-Critical Systems using Relaxed Dedication." In Proceedings of the ACM/IEEE/EDAA/EDAC Conference on Design, Automation and Test in Europe (DATE), Mar. 2011. (pdf)
J. W. Sheaffer. "Physical Challenges in Reliable Graphics Hardware Design." PhD dissertation, Univ. of Virginia School of Engineering and Applied Science, Aug. 2007. Available in pdf.
J. Sheaffer, D. Luebke, and K. Skadron. “A Hardware Redundancy and Recovery Mechanism for Reliable Scientific Computation on Graphics Processors.” In Proceedings of Eurographics/ACM Graphics Hardware 2007 (GH), pp. 55-64, Aug. 2007. (pdf)
Z. Lu, W. Huang, M. Stan, K. Skadron, and J. Lach. “Interconnect Lifetime Prediction for Reliability-Aware Systems.” IEEE Transactions on VLSI Systems, 15(2):159-72, Feb. 2007. (pdf)
Z. Lu. "Runtime Management Techniques for Power- and Temperature-aware Computing." PhD dissertation, Univ. of Virginia School of Engineering and Applied Science, Jan. 2007. Available in pdf.
Z. Lu, W. Huang, M. R. Stan, K. Skadron, and J. Lach. "Interconnect Lifetime Prediction with Temporal and Spatial Temperature Gradients for Reliability-Aware Design and Runtime Management: Modeling and Applications." Tech Report CS-2006-23, Univ. of Virginia Dept. of Computer Science, Oct. 2006. (pdf)
J. W. Sheaffer, D. P. Luebke, and K. Skadron. “The Visual Vulnerability Spectrum: Characterizing Architectural Vulnerability for Graphics Hardware.” In Proceedings of Eurographics/ACM Graphics Hardware 2006, pp. 9-16, Sept. 2006. (pdf)
Z. Lu, J. Lach, M. R. Stan, and K. Skadron. “Improved Thermal Management with Reliability Banking.” IEEE Micro, 25(6):40-49, Nov./Dec. 2005 special issue on Reliability-Aware Microarchitectures. (pdf)
Z. Lu, J. Lach, M. Stan, and K. Skadron. “Temperature-Aware Modeling and Banking of IC Lifetime Reliability.” Tech Report CS-2005-10, Univ. of Virginia Dept. of Computer Science, June 2005.
Z. Lu, J. Lach, M. Stan, and K. Skadron. “Banking Chip Lifetime: Opportunities and Implementation.” In Proceedings of the Workshop on High Performance Computing Reliability Issues (HPCRI), in conjunction with the 11th IEEE International Symposium on High Performance Computer Architecture, Feb. 2005. Available in pdf
Z. Lu, W. Huang, J. C. Lach, M. R. Stan, and K. Skadron. “Interconnect Lifetime Prediction under Dynamic Stress for Reliability-Aware Design.” In Proceedings of the IEEE/ACM International Conference on Computer Aided Design (ICCAD), pp. 327-34, Nov. 2004. Available in pdf
W. Huang, Z. Lu, S. Ghosh, M. Stan, J. Lach, and K. Skadron. “The Importance of Temporal and Spatial Temperature Gradients in IC Reliability Analysis.” Tech Report CS-2004-07, Univ. of Virginia Dept. of Computer Science, Jan. 2004.

Graphics Architecture and GPU Computing

Rodinia Benchmarks Wiki - now version 2.4!

G. Juckeland, W. Brantley, S. Chandrasekaran, B. Chapman, S. Che, M. Colgrove, H. Feng, A. Grund, R. Henschel, W-M. W. Hwu, H. Li, M. S. Mueller, M. Perimov, P. Shelepugin, K. Skadron, J. Stratton, A. Titov, K. Wang, M. van Waveren, B. Whitney, S. Wienke, R. Xu, and K. Kumaran. "SPEC ACCEL: A Standard Application Suite for Measuring Hardware Accelerator Performance." In Proceedings of the Fifth International Workshop on Performance Modeling, Benchmarking and Simulation of High Performance Computer Systems (PMBS14), in conjunction with SC, Nov. 2014.

S. Che and K. Skadron. "BenchFriend: Correlating the Performance of GPU Benchmarks." Sage International Journal of High Performance Computing Applications (IJHPCA), 28(2): 236-248, May 2014. DOI: 10.1177/1094342013507960. (preprint pdf)

M. Boyer, K. Skadron, S. Che, N. Jayasena. "Load Balancing in a Changing World: Dealing with Heterogeneity and Performance Variability. In Proceedings of the ACM Conference on Computing Frontiers, May 2013. (pdf)

M. Boyer, "Improving Resource Utilization in Heterogeneous CPU-GPU Systems" PhD dissertation, Univ. of Virginia School of Engineering and Applied Science, May 2013. (pdf)

C. Gregg, J. Dorn, K. Hazelwood, and K. Skadron. "Fine-Grained Resource Sharing for Concurrent GPGPU Kernels." In Proceedings of the 4th USENIX Workshop on Hot Topics in Parallelism (HotPar), June 2012.

V. Grover, M. Garland, and K. Skadron. “Scalable Manycore Computing with CUDA.” Chapter in Fundamentals of Multicore Software Development, edited by A. Adl-Tabatabi, V. Pankratius, and W. F. Tichy. CRC Press, Nov. 2011.

J. Fix, A. Wilkes, and K. Skadron. "Accelerating Braided B+ Tree Searches on a GPU with CUDA." In Proceedings of the 2nd Workshop on Applications for Multi and Many Core Processors: Analysis, Implementation, and Performance (A4MMC), in conjunction with ISCA, June 2011. (pdf)

M. A. Goodrum, M. J. Trotter, A. Aksel, S. T. Acton, and K. Skadron. Parallelization of Particle Filter Algorithms. In Proceedings of the 3rd Workshop on Emerging Applications and Many-core Architecture (EAMA), in conjunction with the IEEE/ACM International Symposium on Computer Architecture (ISCA), June 2010. Also published with Springer LNCS, volume 6161, "Selected ISCA 2010 Workshops" (pdf of workshop version).

P. Bakkum and K. Skadron. "Accelerating SQL Database Operations on a GPU with CUDA: Extended Results." Tech. Report CS-2010-08, Univ. of Virginia Dept. of Computer Science, May 2010. (pdf) [Also Bakkum's senior thesis, Univ. of Virginia School of Engineering and Applied Science, Apr. 2010.]

P. Bakkum and K. Skadron. "Accelerating SQL Database Operations on a GPU with CUDA." In Proceedings of the Third Workshop on General-Purpose Computation on Graphics Processing Units, Mar. 2010. (pdf)

D. Tarjan, J. Meng, and K. Skadron. "Increasing Memory Miss Tolerance for SIMD Cores." In Proceedings of the ACM/IEEE International Conference for High Performance Computing, Networking, Storage and Analysis (SC), Nov. 2009. Selected as best student paper! (pdf)
S. Che, M. Boyer, J. Meng, D. Tarjan, J. W. Sheaffer, S.-H. Lee, and K. Skadron. “Rodinia: A Benchmark Suite for Heterogeneous Computing.” In Proceedings of the IEEE International Symposium on Workload Characterization (IISWC), pp. 44-54, Oct. 2009. (pdf)
B. Kreuter, R. M. Layer, M. McDaniel, G. Robins, and K. Skadron. "Accelerating Genomic Analysis with Parallel Sliding Windows." Tech. Report CS-2009-14, Univ. of Virginia Dept. of Computer Science, Oct. 2009.
M. A. Guevera, C. Gregg, K. Hazelwood, and K. Skadron. "Enabling Task Parallelism in the CUDA Scheduler." In Proceedings of the Workshop on Programming Models for Emerging Architectures (PMEA), in conjunction with the ACM/IEEE/IFIP International Conference on Parallel Architectures and Compilation Techniques (PACT), Sep. 2009. (pdf)
L. G. Szafaryn, K. Skadron, and J. J. Saucerman. "Experiences Accelerating MATLAB Systems Biology Applications." In Proceedings of the Workshop on Biomedicine in Computing: Systems, Architectures, and Circuits (BiC) 2009, in conjunction with the 36th IEEE/ACM International Symposium on Computer Architecture (ISCA), June 2009. (pdf)

S. Che, M. Boyer, J. Meng, D. Tarjan, S.-H. Lee, J. Sheaffer, and K. Skadron. "Rodinia: A Benchmark Suite for Heterogeneous Computing." Poster session at the 2009 ACM International Symposium on Architectural Support for Programming Languages and Operating Systems (ASPLOS), Mar. 2009. (pdf)

S. Che, M. Boyer, J. Meng, D. Tarjan, J. W. Sheaffer, and K. Skadron. "A Performance Study of General Purpose Applications on Graphics Processors using CUDA." Journal of Parallel and Distributed Computing, Elsevier, 68(10):1370-80, Oct. 2008, DOI http://dx.doi.org/10.1016/j.jpdc.2008.05.014. (UVA final preprint pdf | published pdf)

L. Szafaryn and K. Skadron. "Experience Porting MATLAB Systems Biology Applications to CUDA." NVISION poster session, Aug. 2008. (pdf)

S. Che, M. Boyer, J. Meng, D. Tarjan, J. W. Sheaffer, and K. Skadron. "Experience Porting General-Purpose Applications to GPUs using CUDA." NVISION poster session, Aug. 2008. (pdf)

J. Nickolls, I. Buck, M. Garland, K. Skadron. “Scalable Parallel Programming with CUDA.” ACM Queue, 6(2):40-53, Mar.-Apr. 2008. DOI 10.1145/1365490.1365500 (pdf)

M. Boyer, K. Skadron, and W. Weimer. “Automated Dynamic Analysis of CUDA Programs.” In Proceedings of the Third Workshop on Software Tools for MultiCore Systems (STMCS), in conjunction with the IEEE/ACM International Symposium on Code Generation and Optimization (CGO), Apr. 2008. (pdf)

S. Che, J. Meng, J. W. Sheaffer, and K. Skadron. “A Performance Study of General Purpose Applications on Graphics Processors.” First Workshop on General Purpose Processing on Graphics Processing Units, Northeastern University, Oct. 2007. (pdf)
J. W. Sheaffer. "Physical Challenges in Reliable Graphics Hardware Design." PhD dissertation, Univ. of Virginia School of Engineering and Applied Science, Aug. 2007. Available in pdf.
J. Sheaffer, D. Luebke, and K. Skadron. “A Hardware Redundancy and Recovery Mechanism for Reliable Scientific Computation on Graphics Processors.” In Proceedings of Eurographics/ACM Graphics Hardware 2007 (GH), pp. 55-64, Aug. 2007. (pdf)
K. Dale, J. W. Sheaffer, V. Vijay Kumar, D. P. Luebke, G. Humphreys, and K. Skadron. “Applications of Small-Scale Reconfigurability to Graphics Processors.” International Journal of Electronics, Taylor & Francis, 94(5):549-61, May 2007, DOI 10.1080/00207210701308500. (preprint pdf)
K. Stammetti. "Testing the Feasibility of Running a Computationally Intensive Real-Time Traffic Simulation on a Multicore Programmable Graphics Processor." Senior thesis, Univ. of Virginia School of Engineering and Applied Science, Apr. 2007. (pdf)
P. Sitthi-amorn, “Interactive Three-Dimensional Surface Reconstruction Using the Level Set Method on Parallel Computer Architectures." Senior thesis, Univ. of Virginia School of Engineering and Applied Science, Apr. 2007.
C. Palmer. "Evaluating Reconfigurable Texture Units for Programmable Graphics Cards." Senior thesis, Univ. of Virginia School of Engineering and Applied Science, Apr. 2007. (pdf)
A. Maier. "GPUCT: A GPU-Accelerated CT Reconstruction System." Senior thesis, Univ. of Virginia School of Engineering and Applied Science, Apr. 2007. (pdf)
S. Cook. "Examining Suitability of Multicore Processor Architectures for Solving Realistic Computationally Intensive Problems by Simulating Synaptic Behavior in Large Neural Networks." Senior thesis, Univ. of Virginia School of Engineering and Applied Science, Apr. 2007. (pdf)
A. Banda. "Implementing a Deformable Model Image Segmentation Algorithm for a Multi-Core Microprocessor Architecture." Senior thesis, Univ. of Virginia School of Engineering and Applied Science, Apr. 2007. (pdf)
J. W. Sheaffer, D. P. Luebke, and K. Skadron. “The Visual Vulnerability Spectrum: Characterizing Architectural Vulnerability for Graphics Hardware.” In Proceedings of Eurographics/ACM Graphics Hardware 2006, pp. 9-16, Sept. 2006. (pdf)
K. Dale, J. Sheaffer, V. Vijay Kumar, D. Luebke, G. Humphreys, and K. Skadron. "Applications of Small-Scale Reconfigurability to Graphics Processors." In Proceedings of the International Workshop on Applied Reconfigurable Computing (ARC2006), Springer-Verlag LNCS, pp. 99-108, Mar. 2006. (pdf)
J. W. Sheaffer, K. Skadron. and D. P. Luebke. “Fine-grained Graphics Architectural Simulation with Qsilver.” SIGGRAPH 2005 poster seesion, Aug. 2005.
K. Dale, J. Sheaffer, V. Vijay Kumar, D. Luebke, G. Humphreys, and K. Skadron. “Applications of Small Scale Reconfigurability to Graphics Processors.” Tech Report CS-2005-11, Univ. of Virginia Dept. of Computer Science, June 2005.
D. McWhorter, “Power Consumption Characterization of a Graphics Processing Unit.” Senior thesis, Univ. of Virginia School of Engineering and Applied Science, Apr. 2005. (pdf)
J. W. Sheaffer, K. Skadron, and D. P. Luebke. “Studying Thermal Management for Graphics-Processor Architectures.” In Proceedings of the 2005 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), Mar. 2005. (pdf)
J. W. Sheaffer, D. P. Luebke, and K. Skadron. “Temperature-Aware GPU Design.” SIGGRAPH 2004 poster session, Aug. 2004. (One of 5 semi-finalists for the SIGGRAPH Student Research Competition out of 53 SRC entries and 118 total posters accepted.) Available in pdf [associated video, AVI]
J. W. Sheaffer, D. P. Luebke, and K. Skadron. “A Flexible Simulation Framework for Graphics Architectures.” In Proceedings of Eurographics/ACM Graphics Hardware 2004 (GH), pp. 85-94, Aug. 2004. Available in pdf [associated video, AVI]
N. Goodnight, G. Lewin, D. Luebke, and K. Skadron. “A Multigrid Solver for Boundary-Value Problems Using Programmable Graphics Hardware.” Tech Report CS-2003-03, Univ. of Virginia Dept. of Computer Science, Jan. 2003. Available in pdf (Abstract)

MPEG

Z. Lu, J. Lach, K. Skadron, and M. R. Stan. “Design and Implementation of an Energy Efficient Multimedia Playback System.” In Proceedings of the 40th Asilomar Conference on Signals, Systems and Computers, Oct. 2006. (pdf)
Z. Lu, J. Lach, M.R. Stan, and K. Skadron. "Reducing Multimedia Decode Power using Feedback Control." In Proceedings of the 2003 International Conference on Computer Design, pp. 489-96, Oct. 2003. Available in pdf (Abstract)
Z. Lu, J. Hein, M. Humphrey, M. Stan, J. Lach, and K. Skadron. “Control-Theoretic Dynamic Frequency and Voltage Scaling for Multimedia Workloads.” In Proceedings of the 2002 International Conference on Compilers, Architectures, and Synthesis for Embedded Systems, pp. 156-163, Oct. 2002. Available in postscript or pdf (Abstract)
Z. Lu, J. Hein, M. Humphrey, M. Stan, J. Lach, and K. Skadron. “Control-Theoretic Dynamic Frequency and Voltage Scaling.” In Proceedings of the 2002 Workshop on Self-Healing, Adaptive, and Self-Managed Systems, held in conjunction with ICS 2002, June 2002. (best student paper!) Available in postscript or pdf (Abstract)

Control Theory

T. Horvath and K. Skadron. "Multi-mode Energy Management for Multi-tier Server Clusters." In Proceedings of the ACM/IEEE/IFIP International Conference on Parallel Architectures and Compilation Techniques (PACT), pp. 270-79, Oct. 2008. (pdf | DelayDVS and ClusterControlWare software)
T. Horvath. "Energy Management in Real-Time Multi-Tier Internet Services." PhD dissertation, Univ. of Virginia School of Engineering and Applied Science, May 2008. Available in pdf.
T. Horvath, T. Abdelzaher, and K. Skadron. “Dynamic Voltage Scaling in Multi-tier Web Servers with End-to-end Delay Control.” IEEE Transactions on Computers, 56(4):444-58, Apr. 2007. (pdf)
T. Horvath, T. Abdelzaher, and K. Skadron. “Dynamic Voltage Scaling in Multi-tier Web Servers with End-to-end Delay Control.” Tech Report CS-2004-34, Univ. of Virginia Dept. of Computer Science, Nov. 2004.
K. Sankaranarayanan and K. Skadron. “Profile-Based Adaptation for Cache Decay”. ACM Transactions on Architecture and Code Optimization, 1(3):305-322, Sep. 2004. Available in pdf.
V. Sharma, A. Thomas, T. Abdelzaher, Z. Lu, and K. Skadron. “Power-Aware QoS Management on Web Servers.” In Proceedings of the 24th International Real-Time Systems Symposium, pp. 63-72, Dec. 2003. Available in pdf (Best student paper!)
Z. Lu, J. Lach, M.R. Stan, and K. Skadron. "Reducing Multimedia Decode Power using Feedback Control." In Proceedings of the 2003 International Conference on Computer Design, pp. 489-96, Oct. 2003. Available in pdf (Abstract)
K. Sankaranarayanan. "Profile-Based Adaptation for Cache Decay." MCS project, Univ. of Virginia School of Engineering and Applied Science, Aug. 2003.
Z. Lu, J. Hein, M. Humphrey, M. Stan, J. Lach, and K. Skadron. “Control-Theoretic Dynamic Frequency and Voltage Scaling for Multimedia Workloads.” In Proceedings of the 2002 International Conference on Compilers, Architectures, and Synthesis for Embedded Systems, pp. 156-163, Oct. 2002. Available in postscript or pdf (Abstract)
Z. Lu, J. Hein, M. Humphrey, M. Stan, J. Lach, and K. Skadron. “Control-Theoretic Dynamic Frequency and Voltage Scaling.” In Proceedings of the 2002 Workshop on Self-Healing, Adaptive, and Self-Managed Systems, held in conjunction with ICS 2002, June 2002. (best student paper!) Available in postscript or pdf (Abstract)
S. Velusamy, K. Sankaranarayanan, D. Parikh, T. Abdelzaher, and K. Skadron. “Adaptive Cache Decay using Formal Feedback Control.” In Proceedings of the Workshop on Memory Performance Issues, held in conjunction with ISCA-29, May 2002. Available in postscript or pdf (Abstract)
K. Skadron, T. Abdelzaher, and M. Stan. "Control-Theoretic Techniques and Thermal-RC Modeling for Accurate and Localized Dynamic Thermal Management." In Proceedings of the Eighth International Symposium on High-Performance Computer Architecture, pp. 17-28, Feb. 2002. (Extended version appears as TR CS-2001-27.) Available in postscript or pdf (Abstract) Erratum
K. Skadron, T. Abdelzaher, and M.R. Stan. “Control-Theoretic Techniques and Thermal-RC Modeling for Accurate and Localized Dynamic Thermal Management.” Tech Report CS-2001-27, Univ. of Virginia Dept. of Computer Science, Nov. 2001. (Extended version of HPCA-8 paper.) Available in postscript or pdf (Abstract) Erratum

Branch Prediction and Instruction Fetch

S. W. Chung and K. Skadron. “On-Demand Solution to Minimize I-Cache Leakage Energy with Maintaining Performance.” IEEE Transactions on Computers, 57(1):7-24, Jan. 2008, DOI 10.1109/TC.2007.70770. (pdf)
K. Skadron and D. Tarjan. “Predicting Branches in Computer Programs,” in The Computer Engineering Handbook, 2nd ed., CRC Press, 2007.
M. Co, D. A. B. Weikle, and K. Skadron. "Evaluating Trace Cache Energy Efficiency." ACM Transactions on Architecture and Code Optimization (TACO), 3(4):450-76, Dec. 2006. (Abstract | pdf)
D. Tarjan. "Merging Path, Global and Local Indexing in Perceptron Branch Prediction." MS thesis, Univ. of Virginia School of Engineering and Applied Science, Jan. 2007. (pdf)
S. W. Chung and K. Skadron. "Using Branch Prediction Information for Near-Optimal I-Cache Leakage Reduction." In Proceedings of the 11th Asia-Pacific Systems Architecture Conference (ACSAC), Sept. 2006, pp. 24-37. (pdf)
M. Co. "Designing Energy-Efficient Fetch Engines." PhD dissertation, Univ. of Virginia School of Engineering and Applied Science, Aug. 2006. pdf (Abstract)
S .W. Chung and K. Skadron. “Using Branch Prediction Information for Near-Optimal I-Cache Leakage Reduction.” Tech Report CS-2006-03, Univ. of Virginia Dept. of Computer Science, Mar. 2006. (pdf)
M. Co, D. A. B. Weikle, and K. Skadron. “Potential for Branch Predictor Adaptation at the Program and Phase Level.” Tech Report CS-2005-19, Univ. of Virginia Dept. of Computer Science, Nov. 2005. (pdf)
D. Tarjan and K. Skadron. “Merging Path and Gshare Indexing in Perceptron Branch Prediction.” ACM Transactions on Architecture and Code Optimization, Sept. 2005, 2(3):280-300. (pdf)
M. Co, D. A. B. Weikle, and K. Skadron. “A Break-Even Formulation for Evaluating Branch Predictor Energy Efficiency.” In Proceedings of the 2005 Workshop on Complexity Effective Design (WCED) in conjunction with the 32^nd International Symposium on Computer Architecture (ISCA), June 2005. (pdf)
D. Tarjan and K. Skadron. “Merging Path and Gshare Indexing in Perceptron Branch Prediction.” Tech Report CS-2004-38, Univ. of Virginia Dept. of Computer Science, Dec. 2004.
A. Malaviya, “Applying Kalman Filters to Branch Prediction.” Senior thesis, Univ. of Virginia School of Engineering and Applied Science, Dec. 2004.
M. Co and K. Skadron. "Evaluating Trace Cache Energy-Efficiency." Tech Report CS-2004-31, Univ. of Virginia Dept. of Computer Science, Oct. 2004.
D. Tarjan and K. Skadron. “Revisiting the Perceptron Predictor Again.” Tech Report CS-2004-28, Univ. of Virginia Dept. of Computer Science, Sep. 2004.
D. Tarjan, K. Skadron, and M.R. Stan. “An Ahead Pipelined Alloyed Perceptron with Single Cycle Access Time.” In Proceedings of the 2004 Workshop on Complexity Effective Design, in conjunction with the 31st International Symposium on Computer Architecture (ISCA), June 2004. Available in pdf
D. Parikh, K. Skadron, Y. Zhang, and M. Stan. "Power-Aware Branch Prediction, Characterization and Design." IEEE Transactions on Computers, 53(2):168-86, Feb. 2004. Available in pdf (Abstract)
M. Co and K. Skadron. "Evaluating the Energy Efficiency of Trace Caches." Tech Report CS-2003-19, Univ. of Virginia Dept. of Computer Science, Oct. 2003.
K. R. Hirst, J. W. Haskins Jr., K. Skadron. "dMT: Inexpensive Throughput Enhancement in Small-Scale Embedded Microprocessors with Differential Multithreading: Extended Results." Tech Report CS-2003-18, Univ. of Virginia Dept. of Computer Science, Oct. 2003. (Extended version of Jan. 2004 IEE Proceedings on Computers and Digital Techniques paper.)
Z. Lu, J. Lach, M. Stan, and K. Skadron. “Alloyed Branch History: Combining Global and Local Branch History for Robust Performance,” International Journal of Parallel Programming, Kluwer, 31(2):137-77, Apr. 2003. Available in pdf (Abstract)
D. Parikh. "Power Aware Branch Prediction: Characterization and Design." MCS project, Univ. of Virginia School of Engineering and Applied Science, Jan. 2003. Available in pdf
Z. Hu, P. Juang, K. Skadron, D. Clark, and M. Martonosi. “Applying Decay Strategies to Branch Predictors for Leakage Energy Savings.” In Proceedings of the 2002 International Conference on Computer Design, pp. 442-45, Sept. 2002. Available in pdf (Abstract)
Z. Hu, P. Juang, S. Kaxiras, P. Diodato, K. Skadron, D.W. Clark, and M. Martonosi. “Managing Leakage for Transient Data : Decay and Quasi-Static Memory Cells.” In Proceedings of the 2002 International Symposium on Low-Power Electronics and Design, Aug. 2002. Available in pdf (Abstract)
Z. Lu, J. Lach, M.R. Stan, and K. Skadron. “Alloyed Branch History: Combining Global and Local Branch History for Robust Performance,” Tech Report CS-2002-21, Univ. of Virginia Dept. of Computer Science, July 2002. Available in postscript (Abstract) -- superseded by a paper with the same title appearing in the International Journal of Parallel Programming, Kluwer, volume 31, number 2, Apr. 2003, see above.
D. Parikh, K. Skadron, Y. Zhang, M. Barcella, and M. Stan. "Power Issues Related to Branch Prediction." In Proceedings of the Eighth International Symposium on High-Performance Computer Architecture, pp. 233-44, Feb. 2002. (Extended version appears as TR CS-2001-25.) Available in postscript or pdf (Abstract)
K. Skadron. “Predicting Branches in Computer Programs,” in The Computer Engineering Handbook, CRC Press, 2002.
D. Parikh, K. Skadron, Y. Zhang, M. Barcella, and M. Stan. “Power Issues Related to Branch Prediction.” Tech Report CS-2001-25, Univ. of Virginia Dept. of Computer Science, Nov. 2001. (Extended version of HPCA-8 paper.) Available in pdf (Abstract)
Z. Hu, P. Juang, K.Skadron, M. Martonosi, and D. W. Clark. “Applying Decay Strategies to Branch Predictors for Leakage Energy Savings.” Tech Report CS-2001-24, Univ. of Virginia Dept. of Computer Science, Oct. 2001. Available in pdf (Abstract)
M. Co and K. Skadron. "The Effects of Context Switching on Branch Predictor Performance." In Proceedings of the 2001 IEEE International Symposium on Performance Analysis of Systems and Software, pp. 77-84, Nov. 2001. Available in postscript or pdf (Abstract)
K. Sankaranarayanan and K. Skadron. “A Scheme for Selective Squash and Re-issue for Single-Sided Branch Hammocks.” In Proceedings of the Work-in-Progress Session at the 2001 International Conference on Parallel Architectures and Compilation Techniques, Sept. 2001. Also appears in Newsletter of the IEEE Technical Committee on Computer Architecture, pp. 4-5, Oct. 2001. Available in pdf
K. Sankaranarayanan and K. Skadron. "A Scheme for Selective Squash and Re-issue for Single-Sided Branch Hammocks." Tech Report CS-2001-14, Univ. of Virginia Dept. of Computer Science, July, 2001. Available in pdf (Abstract)
M. Co. "The Effects of Context Switching on Branch Predictor Performance." MCS project, Univ. of Virginia School of Engineering and Applied Science, June 2001. Available in postscript
J.C. Ablutz. "Analyzing and Improving Alloyed Branch Predictor Performance." Senior thesis, Univ. of Virginia School of Engineering and Applied Science, Apr. 2001. Available in Word
S. Kelley. "Branch and Confidence Prediction with Perceptrons." Senior thesis, Univ. of Virginia School of Engineering and Applied Science, Apr. 2001. Available in Word
K. Skadron, M. Martonosi, and D.W. Clark. "A Taxonomy of Branch Mispredictions, and Alloyed Prediction as a Robust Solution to Wrong-History Mispredictions." In Proceedings of the 2000 International Conference on Parallel Architectures and Compilation Techniques, pp. 199-206, Oct. 2000. Available in postscriptor pdf (Abstract)
P. Juang. "Classification-based Hybrid Branch Prediction." Senior thesis, Univ. of Virginia School of Engineering and Applied Science; also Dept. of Computer Science Tech. Report CS-2000-15; Mar. 2000. Available in postscript (Abstract)
A.V. Lanning. "Pipelined Branch Prediction: Characterizing Wrong-History Misprediction." Senior thesis, Univ. of Virginia School of Engineering and Applied Science; Apr. 2000. Available in Word
K. Skadron, M. Martonosi, and D.W. Clark. "Speculative Updates of Local and Global Branch History: A Quantitative Analysis." Journal of Instruction-Level Parallelism, vol. 2, Jan. 2000(http://www.jilp.org/vol2). Available in postscript (Abstract)
K. Skadron, P.S. Ahuja, M. Martonosi, and D.W. Clark. "Branch Prediction, Instruction-Window Size, and Cache Size: Performance Tradeoffs and Simulation Techniques." IEEE Transactions on Computers, 48(11):1260-81, Nov. 1999. Available in pdf (Abstract)
K. Skadron, M. Martonosi, and D.W. Clark. "Alloying Global and Local Branch History: A Robust Solution to Wrong-History Mispredictions." Tech Report TR-606-99, Princeton Dept. of Computer Science, Oct. 1999. Available in postscript (Abstract)
K. Skadron. "Characterizing and Removing Branch Mispredictions." PhD dissertation, Princeton Univ.; also Tech. Report TR-604-99; June 1999. Available in gzip'd postscript or PDF. (Abstract)
K. Skadron, M. Martonosi, and D.W. Clark. "Alloying Global and Local Branch History: Taxonomy, Performance, and Analysis." Tech Report TR-594-99, Princeton Dept. of Computer Science, Jan. 1999. Available in postscript (Abstract)
K. Skadron, P.S. Ahuja, M. Martonosi, and D.W. Clark. "Improving Prediction for Procedure Returns with Return-Address-Stack Repair Mechanisms." In Proceedings of the 31st Annual ACM/IEEE International Symposium on Microarchitecture, pp. 259-71, December 1998. Available in postscript or pdf (Abstract)
P.S. Ahuja, K. Skadron, M. Martonosi, and D.W. Clark. "Multipath Execution: Opportunities and Limits." In Proceedings of the 1998 International Conference on Supercomputing, pp. 101-08, July 1998. Available in postscript or pdf (Abstract)

Caching and Write Buffers

J. Mars, L. Tang, R. Hundt, K. Skadron, and M. L. Soffa. "Bubble-Up: Increasing Utilization in Modern Warehouse Scale Computers via Sensible Co-locations." IEEE Micro, special issue on Top Picks from 2011 Architecture Conferences).

J. Mars, L. Tang, R. Hundt, K. Skadron, and M. L. Soffa. "BubbleUp: Increasing Sensible Co-locations for Improved Utilization in Modern Warehouse Scale Computers." In Proceedings of the ACM/IEEE International Symposium on Microarchitecture (MICRO), Dec. 2011. (pdf)

J. Meng. "Breaking the Memory Wall for Highly Multi-Threaded Cores." PhD dissertation, Univ. of Virginia School of Engineering and Applied Science, Aug. 2010. Available in pdf.

J. Meng and K. Skadron “Avoiding Cache Thrashing due to Private Data Placement in Last-Level Cache for Manycore Scaling.” In Proceedings of the IEEE International Conference on Computer Design (ICCD), pp. 282-88, Oct. 2009. (pdf)
K. Sankaranarayanan and K. Skadron. “Profile-Based Adaptation for Cache Decay”. ACM Transactions on Architecture and Code Optimization, 1(3):305-322, Sep. 2004. Available in pdf.
K. Sankaranarayanan. "Profile-Based Adaptation for Cache Decay." MCS project, Univ. of Virginia School of Engineering and Applied Science, Aug. 2003.
S. Velusamy, K. Sankaranarayanan, D. Parikh, T. Abdelzaher, and K. Skadron. “Adaptive Cache Decay using Formal Feedback Control.” In Proceedings of the Workshop on Memory Performance Issues, held in conjunction with ISCA-29, May 2002. Available in postscript or pdf (Abstract)
A. Spanberger, “Designing a Dynamically Reconfigurable Cache for High Performance and Low Power.” Senior thesis, Univ. of Virginia School of Engineering and Applied Science, Apr. 2002 (finalist in the 2002 SEAS Undergraduate Research and Design Symposium). Available in pdf
M. Ziegler, A. Spanberger, G. Pai, M. Stan, and K. Skadron. “Dynamic Way Allocation for High Performance, Low Power Caches.” In Proceedings of the Work-in-Progress Session at the 2001 International Conference on Parallel Architectures and Compilation Techniques, Sept. 2001. Also appears in Newsletter of the IEEE Technical Committee on Computer Architecture, pp. 14-15, Oct. 2001. Available in pdf
D.A.B. Weikle. "A Framework for the Analysis of Caching Systems." PhD dissertation, Univ. of Virginia School of Engineering and Applied Science, Apr. 2001. Available in postscript or pdf (Abstract)
D.A.B. Weikle, K. Skadron, S.A. McKee, and W.A. Wulf. "TSpec: A Notation for Describing Memory Reference Traces." Tech Report CS-2000-23, Univ. of Virginia Dept. of Computer Science, Aug. 2000. Available in postscript (Abstract)
D.A.B. Weikle, K. Skadron, S.A. McKee, and W.A. Wulf. "Caches As Filters: A Unifying Model for Memory Hierarchy Analysis." Tech Report CS-2000-16, Univ. of Virginia Dept. of Computer Science, June, 2000. Available in postscript (Abstract)
D.A.B. Weikle, S.A. McKee, K. Skadron, and W.A. Wulf. "Caches as Filters: A Framework for the Analysis of Caching Systems." In Proceedings of the Third Grace Hopper Celebration of Women in Computing Conference - 2000, Sept. 2000. Available in pdf (Abstract)
K. Skadron and D.W. Clark. "Design Issues and Tradeoffs for Write Buffers." In Proceedings of the Third International Symposium on High-Performance Computer Architecture, pp. 144-55, February 1997. Available in postscript or pdf (Abstract)
K. Skadron and D.W. Clark. "Measuring the Effects of Retirement and Load-Service Policies on Write Buffer Performance." In Proceedings of the 1996 Workshop on Performance Analysis and its Impact on Design (PAID), March 1996. An index of papers pertaining to write buffers

Performance Tradeoffs and Simulation Methodology

ArchFP software
Rodinia Benchmarks Wiki
Genetically Programmed Response Surfaces Toolkit
AmberBBV, for generating basic block vectors (e.g. for use with SimPoint) from Amber traces (part of the CHUD tools).
Qsilver home page
MRRL home page
Hydrascalar home page
G. Juckeland, W. Brantley, S. Chandrasekaran, B. Chapman, S. Che, M. Colgrove, H. Feng, A. Grund, R. Henschel, W-M. W. Hwu, H. Li, M. S. Mueller, M. Perimov, P. Shelepugin, K. Skadron, J. Stratton, A. Titov, K. Wang, M. van Waveren, B. Whitney, S. Wienke, R. Xu, and K. Kumaran. "SPEC ACCEL: A Standard Application Suite for Measuring Hardware Accelerator Performance." In Proceedings of the Fifth International Workshop on Performance Modeling, Benchmarking and Simulation of High Performance Computer Systems (PMBS14), in conjunction with SC, Nov. 2014.
G. Faust, R. Zhang, K. Skadron, M.R. Stan, and B. Meyer. "ArchFP: Rapid Prototyping of pre-RTL Floorplans." In Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), Oct. 2012. (pdf | ArchFP software)
G. Faust, B. H. Meyer, and K. Skadron. "Rapid Prototyping of CMP Floorplans: A Technical Report." Tech. Report CS-2012-02, Univ. of Virginia Dept. of Computer Science, Mar. 2012. (pdf)
W. Heirman, T. E. Carlson, S. Che, K. Skadron, and L. Eeckhout. "Using Cycle Stacks to Understand Scaling Bottlenecks in Multi-Threaded Workloads" In Proceedings of the IEEE International Symposium on Workload Characterization (IISWC), Nov. 2011. (pdf)
J. Meng and K. Skadron. "A Reconfigurable Simulator for Large-scale Heterogeneous Multicore Architectures." In Proceedings of the 2011 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), pp. 119-120, Mar. 2011. (pdf | poster | MV5 website)
S. Che, J. W. Sheaffer, M. Boyer, L. G. Szafaryn, L. Wang, and K. Skadron. "A Characterization of the Rodinia Benchmark Suite with Comparison to Contemporary CMP Workloads." In Proceedings of the IEEE International Symposium on Workload Characterization (IISWC), Dec. 2010. (pdf)
S. Che, M. Boyer, J. Meng, D. Tarjan, J. W. Sheaffer, S.-H. Lee, and K. Skadron. “Rodinia: A Benchmark Suite for Heterogeneous Computing.” In Proceedings of the IEEE International Symposium on Workload Characterization (IISWC), pp. 44-54, Oct. 2009. (pdf)
H. Cook and K. Skadron. “Predictive Design Space Exploration Using Genetically Programmed Response Surfaces.” In Proceedings of the ACM/IEEE Conference on Design Automation (DAC), June 2008. (pdf | Genetically Programmed Response Surfaces Toolkit software)
H. Cook and K. Skadron. "Genetically Programmed Response Surfaces for Efficient Design Space Exploration" Univ. of Virginia Dept. of Computer Science Tech. Report CS-2007-12, Aug. 2007. (pdf)
H. Cook. "Optimizing Chip Multiprocessor Designs Using Genetically Programmed Response Surfaces" Senior thesis, Univ. of Virginia School of Engineering and Applied Science, Apr. 2007. (Awarded first place in the 2007 UVA SEAS Undergraduate Research and Design Symposium) (pdf)
J. Meng, H. Cook, K. Skadron, and D. A. B. Weikle. “Comparing Doom 3, WarCraft III, PBRT, and MESA Using Micro-architecturally Independent Characteristics.” Tech Report CS-2007-04, Univ. of Virginia Dept. of Computer Science, Feb. 2007. (pdf)
P. Sitthi-Amorn, D. A. B. Weikle, and K. Skadron. “Exploring the Impact of Normality and Significance Te sts in Architecture Experiments.” In Proceedings of the 2006 Workshop on Modeling, Benchmarking and Simulation, in conjunction with the 33rd International Symposium on Computer Architecture (ISCA ), June 2006. (pdf)
Y. Li, M. Hempstead, P. Mauro, D. Brooks, Z. Hu, and K. Skadron. “Power and Thermal Effects of SRAM vs. LatchMux Design.” In Proceedings of the ACM/IEEE 2005 International Symposium on Low-Power Electronics Design (ISLPED), pp. 173-178, Aug. 2005. (pdf)
J.W. Haskins, Jr. and K. Skadron. “Accelerated Warmup for Sampled Microarchitecture Simulation.” ACM Transactions on Architecture and Compiler Optimization, 2(1):78-108, Mar. 2005. (pdf)
K.-J. Lee and K. Skadron. “Using Performance Counters for Runtime Temperature Sensing in High-Performance Processors.” In Proceedings of the Workshop on High-Performance, Power-Aware Computing (HP-PAC), in conjunction with the 2005 International Parallel and Distributed Processing Symposium, Apr. 2005. Available in pdf [Presentation slides pdf]
Y. Li, D. Brooks, Z. Lu, and K. Skadron. “Power and Thermal Effects of Different Clock Gating Schemes in General Purpose Processors.” Poster and associated paper at the IBM Austin Conference on Energy-Efficient Design (ACEED), Mar. 2005.
S. Velusamy, W. Huang, J. Lach, M. Stan, and K. Skadron. “Experiences using FPGAs for Temperature-Aware Microarchitecture Research.” In the 2005 Workshop on Architecture Research using FPGA Platforms (WARFP), in conjunction with the 11th IEEE International Symposium on High Performance Computer Architecture, Feb. 2005. Available in pdf
J. W. Sheaffer, D. P. Luebke, and K. Skadron. “A Flexible Simulation Framework for Graphics Architectures.” In Proceedings of the Eurographics/ACM Graphics Hardware 2004 (GH), pp. 85-94, Aug. 2004. Available in pdf [associated video, AVI] [Qsilver software home page]
K. Skadron, M. Martonosi, D. I. August, M. D. Hill, D. J. Lilja, and V. S. Pai. "Challenges in Computer Architecture Evaluation." IEEE Computer, Aug. 2003. Available in pdf (Abstract)
J. W. Haskins, Jr. "Accelerating Sampled Microarchitecture Simulation: Rapid Warm Up for Simulated Hardware State." PhD dissertation, Univ. of Virginia School of Engineering and Applied Science, May 2003. Available in pdf
Y. Zilbergleyt, "Finding and Characterizing New Benchmarks for Computer Architecture Research." Senior thesis, Univ. of Virginia School of Engineering and Applied Science, Apr. 2003. Available in pdf
J.W. Haskins, Jr. and K. Skadron. “Memory Reference Reuse Latency: Accelerated Sampled Microarchitecture Simulation.” In Proceedings of the 2003 IEEE International Symposium on Performance Analysis of Systems and Software, pp. 195-203, Mar. 2003. Available in postscript or pdf (Abstract) [software home page]
J. W. Haskins, Jr. and K. Skadron. “Memory Reference Reuse Latency: Accelerated Sampled Microarchitecture Simulation.” Tech Report CS-2002-19, Univ. of Virginia Dept. of Computer Science, July 2002. Available in postscript (Abstract) -- superseded by a paper with the same title appearing in Proceedings of the 2003 IEEE International Symposium on Performance Analysis of Systems and Software, Mar. 2003, see above.
E. Bauer, “Examination of a Novel Method of Emulating System Calls in Microprocessor Simulators.” Senior thesis, Univ. of Virginia School of Engineering and Applied Science, Apr. 2002. Available in Word
J. W. Haskins, Jr., A. J. KleinOsowski, K. Skadron, and D. J. Lilja. "Techniques for Accurate, Accelerated Processor Simulation: Analysis of Reduced Inputs and Sampling." Tech Report CS-2002-01, Univ. of Virginia Dept. of Computer Science, Jan. 2002. Available in postscript (Abstract)
J.W. Haskins and K. Skadron. "Minimal Subset Evaluation: Rapid Warm-up for Simulated Hardware State." In Proceedings of the 2001 International Conference on Computer Design, pp. 32-39, Sept. 2001. Available in pdf (Abstract)
S.K. Chan. "Building and Distributing a Next-Generation Benchmark Suite for Computer Research." Senior thesis, Univ. of Virginia School of Engineering and Applied Science, Apr. 2001. Available in Word (supporting data)
K. Skadron and P.S. Ahuja. "HydraScalar: A Multipath-Capable Simulator." In the Newsletter of the IEEE Technical Committee on Computer Architecture, pp. 65-70, Jan. 2001. Available in postscript or pdf (Abstract) [software home page]
K. Skadron, P.S. Ahuja, M. Martonosi, and D.W. Clark. "Branch Prediction, Instruction-Window Size, and Cache Size: Performance Tradeoffs and Simulation Techniques." IEEE Transactions on Computers, 48(11):1260-81, Nov. 1999. Available in pdf (Abstract)
K. Skadron, P.S. Ahuja, M. Martonosi, and D.W. Clark, "Selecting a Single, Representative Sample for Accurate Simulation of SPECint Benchmarks." Tech Report TR-595-99, Princeton Dept. of Computer Science, Jan. 1999. Available in gzip'd postscript or pdf (Abstract)

Miscellaneous

M. El-Hadedy, K. Skadron, H. Mihajloska, and D. Gligorski. “Programmable Processing Element for Crypto-Systems on FPGAs.” In Proceedings of the International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART), June 2015. (pdf)

R. Sarkar, S. Ozer, S. Acton, and K. Skadron. "Robust Image Recognition by Multi-Kernel Dictionary Learning." Invited paper, In Proceedings of the Asilomar Conference on Signals, Systems and Computers, Nov. 2014.

R. Sarkar, K. Skadron, and S. Acton. "A Meta-Algorithm for Classification by Feature Nomination." In Proceedings of the IEEE International Conference on Image Processing, Oct. 2014. (preprint pdf)

M. Salajegheh, K. Skadron, and M. R. Stan. "Low-Voltage NAND Flash without Hardware Modifications." Poster and extended abstract, IEEE Non-Volatile Memory Technology Symposium, Oct. 2014. (submitted abstract)

F. Wu, J. Wadden, J. Lach, K. Skadron, and J. Saucerman. "Gene Expression from the Gq Transgenic Mouse is Sufficient to Mechanistically Predict Altered Cardiac EC coupling." Abstract, Biomedical Engineering Society Annual Meeting, Sept. 2013.

R. M. Layer, K. Skadron, G. Robins, I. M. Hall, and A. R. Quinlan. "Binary Interval Search: A Scalable Algorithm for Counting Interval Intersections. Bioinformatics 29(1):1-7, Jan. 2013. (preprint pdf)

M. D. Marino and K. Skadron. "Reducing Power and Area by Interconnecting Memory Controllers to Memory Ranks with RF Coplanar Waveguides on the Same Package." In Proceedings of the 3rd Workshop on Energy-Efficient Design (WEED), in conjunction with ISCA, June 2011. (pdf)

M. Marino, G. Robins, K. Skadron, and L. Wang. "Bridging the Gap Between Theory and Hardware." Abstract and presentation at the "Wild and Crazy Ideas" session at ASPLOS, Mar. 2010. (pdf)
D. Grosvenor. "Detection and Tracking of Human Subjects." Senior thesis, Univ. of Virginia School of Engineering and Applied Science, Apr. 2009. (pdf)
J. Meng, D. A. B. Weikle, G. Humphreys, and K. Skadron. “An Approach on Hardware Design for Computational Photography.” Tech. Report CS-2007-15, Univ. of Virginia Dept. of Computer Science, Nov. 2007. (pdf)
A. Mukherjee, “Development of Visualization Tools for . Mukherjee and K. Skadron. “Measuring Parameter Variation on an FPGA Using Ring Oscillators.” Tech Report CS-2006-16, Univ. of Virginia Dept. of Computer Science, June 2006. (pdf)
A. Mukherjee, “Development of Visualization Tools for Out-of-Order Execution Simulators.” Senior thesis, Univ. of Virginia School of Engineering and Applied Science, Apr. 2005. (pdf)
P. Dadvar, “Security Threats of Power and Thermal Control Intefaces.” Senior thesis, Univ. of Virginia School of Engineering and Applied Science, Apr. 2005. (pdf)
P. Dadvar and K. Skadron. “Potential Thermal Security Risks.” In Proceedings of the IEEE Semiconductor Thermal Measurement, Modeling, and Management Symposium (Semi-Therm 21), pp. 229-34, Mar. 2005. Available in pdf
K. Hirst. "Hardware Support for SDT: The Use of Hardware Counters for Hot Spot Detection in Strata." MCS project, Univ. of Virginia School of Engineering and Applied Science, June 2002. Available in pdf
M.R. Stan and K. Skadron. “Teaching Processor Architecture with a VLSI Perspective.”
In Proceedings of the Workshop on Computer Architecture Education (WCAE), in conjunction with ISCA-29, May 2002.J. Erdman, “Lighting Integrated Technology: Improvements to a Dynamic Theater System.” Senior thesis, Univ. of Virginia School of Engineering and Applied Science, Apr. 2002 (featured in the University Undergraduate Research Symposium).
P. Lamanna, “Adaptive Security Policies Enforced by Software Dynamic Translation.” Senior thesis, Univ. of Virginia School of Engineering and Applied Science, Apr. 2002. Available in pdf
K. Skadron. "A Microprocessor Survey Course for Learning Advanced Computer Architecture." In Proceedings of the 2002 SIGCSE Symposium, pp. 152-56, Feb.-Mar. 2002. Available in postscript or pdf (Abstract)
K. Skadron, M. Humphrey, B. Huang, E. Hilton, J. Luo, and P. Allaire. "The Use of Mini-Vector Instructions for Implementing High-Speed Feedback Controllers on General-Purpose Computers." In Proceedings of the 3rd Workshop on Media and Stream Processors, in conjunction with MICRO-34, Dec. 2001. Available in postscript or pdf (Abstract)
K. Skadron, M. Humphrey, B. Huang, E. Hilton, J. Luo, and P. Allaire. “Supporting Higher-Order Controllers for Magnetic Bearings in a High-Speed, Real-Time Platform Using General-Purpose Computers.” In Proceedings of the 2001 International Symposium on Magnetic Suspension Technology, Oct. 2001. Available in pdf (Abstract)
K. Scott, K. Skadron, and J. W. Davidson. “Low-Overhead Software Dynamic Translation.” Tech Report CS-2001-18, Univ. of Virginia Dept. of Computer Science, Sept. 2001. Available in pdf (Abstract)
J. Miranda. "The Usage of Compiler Optimization by Programmers: A Sociological Study of the Extent of Their Use and the Rationales Behind this Usage." Senior thesis, Univ. of Virginia School of Engineering and Applied Science, Apr. 2001. Available in Word
K. Scott and K. Skadron. "BLP: Applying ILP Techniques to Bytecode Execution." In Proceedings of the Second Annual Workshop on Hardware Support for Objects and Microarchitectures for Java, in conjunction with ICCD 2000, Sept. 2000. Available in postscript or pdf (Abstract)
K. Skadron. "A Microprocessor Survey Course: Exploring Advanced Computer Architecture in Practice." In Proc. of the Workshop on Computer Architecture Education, in conjunction with ISCA-27, June 2000. Available in postscript or pdf (Abstract)
B.S. White and K. Skadron. "Path-Based Target Prediction for File System Prefetching." Tech Report CS-2000-06, Univ. of Virginia Dept. of Computer Science, June, 2000. Available in postscript (Abstract)
K. Skadron, S.A. Watson, and K.H. Mueller. "A Study of Spectral Effects Using Synthetic Radiography." Los Alamos Unclassified Report LAUR 944247, Los Alamos National Laboratory, Dec. 1994. (Abstract)

Patents

D. Tarjan and K. Skadron, "Policy based allocation of register file cache to threads in multi-threaded processor." US Patent 8,200,949, June 2012.
D. Tarjan and K. Skadron, "System, method, and computer program product for removing a register of a processor from an active state," US Patent 8,078,844, Dec. 2011.

Software Releases

MNRL - a specification language for finite state machines
MNCaRT - an end-to-end research toolkit for automata processing across multiple processing platforms
ATR - Automata-to-routing - an adaptation of VPR for automata processing on spatial architectures
VASim - An engine for cross-platform automata processing, supporting CPU, FGPA, Micron AP, and coming soon, GPU
iNFAnt2 - a GPU NFA execution engine
ANMLZoo - A benchmark suite for automata processing
RAPID - a C-like programming language for inexact pattern matching
VoltSpot software - now version 2!
HotSpot software - now version 6!
HotLeakage software
ArchFP software
Rodinia Benchmarks Wiki - now version 3!
Lumos
MV5 simulator - a modification of M5 supporting SIMD and multithreaded architectures
DelayDVS and ClusterControlWare - software for power management in multi-tier servers
Genetically Programmed Response Surfaces Toolkit
AmberBBV, for generating basic block vectors (e.g. for use with SimPoint) from Amber traces (part of the CHUD tools).
Qsilver
MRRL tools
HydraScalar

Kevin's home page
Last updated 17 July 2017

This work is currently supported by the National Science Foundation under grant no. CCF-1629450 (XPS) and CCF-1619127; by DARPA MTO (PERFECT program) under contract HR0011-13-C-0022; by C-FAR, one of six centers of STARnet, a Semiconductor Research Corporation program sponsored by MARCO and DARPA; the Virginia CIT CRCF program under grant MF16-032-IT; Xilinx; an ARCS Scholarship for Jack Wadden; and equipment donations and extended loans from Micron and Xilinx. The U.Va. Center for Automata Processing (CAP) is supported in part by Micron.