Hello John;
Were you yet able to run the STREAM program on the SX-3? I am very
curious about the multiple CPU runs.
There is much confusion as to how the SX-3 memory system works. I have
even asked NEC analysts at the IEEE Supercomputing conferences and each
one gives a different description. I think that your test could shed
light of this confusion.
The overall NEC SX-3 CPU-memory system is represented in the figure
below. (I obtained this diagram from an NEC systems analyst at the
Canadian Met site.) Each vector unit has three paths to the Main
Memory Interface (MMI). The width of each path is related to the
number of pipe sets in each CPU. For example, a four pipe set system
has paths that are four 64-bit words wide.
------------- |---| +-------+
| | | |==>| |
| | | | | CPU 0 |
| | | |<--| |
| |=====| | +-------+
| MMU 0 | | |
| |-----| | +-------+
| | | |==>| |
| | | | | CPU 1 |
| | | |<--| |
| | | M | +-------+
------------- | M |
------------- | I |
| | | | +-------+
| | | |==>| |
| | | | | CPU 0 |
| | | |<--| |
| |=====| | +-------+
| MMU 1 | | |
| |-----| | +-------+
| | | |==>| |
| | | | | CPU 1 |
| | | |<--| |
------------- |---| +-------+
NEC SX-3/44R Memory Architecture.
The MMI has two sets of three paths to the two individual Main
Memory Units (MMUs). We do not know what is the bandwidth of these
paths. The STREAM test program should be able to resolve the width of
each path to memory.
Regards,
Charles Grassl
Cray Research, Inc.
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