In article <m4dh1bINNnee@exodus.Eng.Sun.COM> tremblay@flayout.Eng.Sun.COM (Marc Tremblay) writes:
>In article <1993Jul16.104143.27476@is.titech.ac.jp> maeno@is.titech.ac.jp (Toshinori Maeno) writes:
>> 2. read miss penalty is 12 cycles for read, 40 cycles for write when
>>the data is only in the memory.
>
>At 133 MHz, 12 cycles represent 90ns. Given the size of main memory
>(the SPEC92 numbers were obtained on a machine with 128 MB), 90ns for
>the miss processing and for main memory latency would put tough
>constraints on the DRAMs. I suspect that 12 cycles are what is measured
>from address out to data in and does not include the overhead for
>the miss handling and bringing the data into the pipeline.
>
>Maybe someone from DEC can explain the discrepancy between the 12 cycles
>claimed here and the 27 cycles that was claimed in a previous message
>for a second level read miss.
>Sun Microsystems.
I am very sorry, I was confused and made a second mistake.
>> 2. read miss penalty is 12 cycles for read, 40 cycles for write when
==
33 was the measured cycles.
>>the data is only in the memory.
Toshinori Maeno
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