Re: Stride Stream benchmark

From: P Dickerson (peter@localhost)
Date: Sun Dec 27 1998 - 07:28:43 CST

Results for 225 MHz AMD K6 in TX MoBo and 75 MHz bus clock, 64MB SDRAM, NT4
SP3
#include <sys/times.h> needed to be commented out, source saved as tlb.c.
Note pagesize for x86 is 4K, line size is 32 for Pentium and Pentium II
class machines.

D:\MYAPPS\MSVC\TLB> cl /Ox -DPAGESIZE=4096 -DCACHELINE=32 tlb.c
Microsoft (R) 32-bit C/C++ Optimizing Compiler Version 12.00.8168 for 80x86
Copyright (C) Microsoft Corp 1984-1998. All rights reserved.

tlb.c
Microsoft (R) Incremental Linker Version 6.00.8168
Copyright (C) Microsoft Corp 1992-1998. All rights reserved.

/out:tlb.exe
tlb.obj

D:\MYAPPS\MSVC\TLB> tlb
STRIDE STREAM BENCHMARK. Stride size is 4136 bytes.
   Copyright 1998 Naohiko Shimizu<nshimizu@et.u-tokai.ac.jp>
Please report the result with your system.

Transfer size(B) Throughput(MB/S) Access Time(nS)
          136 612.000 13
          264 586.667 14
          520 581.366 14
         1032 402.078 20
         2056 71.610 112 

--
P.M.Dickerson.
email: peter (at) izabella (dot) demon (dot) co (dot) uk

pshimizu@fa2.so-net.ne.jp wrote in message
<763ac2$o36$1@news01bf.so-net.ne.jp>...
>Hi,
>This is a benchmark program to check the system's stride memory access
>performance. Even in cache, most of RISC machines has poor performance
>for a large stride data transfer, because of shorttage of the TLB
>entries. With this program you can check the out of TLB performance.
>
>Enjoy,
>Naohiko Shimizu.
>
>===========================================================================
==
>/*
>STRIDE STREAM BENCHMARK PROGRAM                   Last updated date :
98.12.26
>
>Copyright 1998 by Naohiko Shimizu <nshimizu@et.u-tokai.ac.jp>
>All rights reserved.
>
>See GNU Public License 2.0 for the licensing term.
>
>Many system has poor performance on a large stride problem. This program
>will test your system's IN CACHE stride access performance. The inner most
>loop is designed to fit in almost all processors 1st cache.
>If you have 16KB 1st cache and 32 bytes cache line size, upto 512 bytes
>stride transfer will fit in your cache. (16*1024/32)
>If you have more knowledge about your system, you can set CACHELINE and
>PAGESIZE parameters for more accurate results.
>
>This program is designed with clock() function of C language, and if the
>running time is too short for clock tick the result may not be correct.
>
>================= example result for AS200 4/100
===========================
>alpha% cc -O2 -o strdstrm -DCACHELINE=32 -DPAGESIZE=8192 strdstrm.c
>alpha% ./strdstrm
>STRIDE STREAM BENCHMARK. Stride size is 8232 bytes.
>   Copyright 1998 Naohiko Shimizu<nshimizu@et.u-tokai.ac.jp>
>Please report the result with your system.
>
>Transfer size(B)   Throughput(MB/S)    Access Time(nS)
>          136         816.000           10
>          264          24.122          332
>          520          24.124          332
>         1032          24.125          332
>         2056          22.873          350
>===========================================================================
>
>
>Contact information:
>
>Dr. Naohiko Shimizu
>School of Engr. Tokai Univ.
>1117 Kitakaname Hiratsuka
>Kanagawa 259-1292 Japan
>email: nshimizu@et.u-tokai.ac.jp
>URL: http://shimizu-lab.et.u-tokai.ac.jp
>

[ Source snipped]

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