The goal of this course is to provide students with a modern view of computer architecture, and introduce them to the latest developments, challenges, issues, risks, and trends that drive the modern microprocessor industry. By taking this course, students will:

• become conversant with fundamental computer architecture concepts,
• be able to read and evaluate specs of modern architectures,
• understand state-of-the-art design mechanisms and optimizations, and their implications on performance, power efficiency, and security, and
• learn how to craft attacks that exploit security vulnerabilities in modern processors.

Required Textbook:

Hennessy and Patterson, "Computer Architecture: A Quantitative Approach", Sixth Edition

Other (frequently referenced) online resources:

• Books from Synthesis Lectures on Computer Architecture
• Papers from top architecture conferences and journals, as assigned.

Contact

We will use Piazza as our class forum, and our primary mode of communication outside of class. All general inquiries must be made on Piazza. For group-specific questions or private questions, you can either email me or post a private question on Piazza.

Instructor:

Ashish Venkat (email: <lastname>@virginia.edu)
Office Hours: Mo/We 11am-12pm @ Rice 312, or by appointment.

Teaching Assistants:

Logan Moody (email: lgm4xn@virginia.edu)
Office Hours: Tu/Th 11am-12pm @ Rice 442

Conner Ward (email: cjw5db@virginia.edu)
Office Hours: We 2pm-3pm @ Rice 442

Prerequisites

This is a graduate class -- we will be exploring advanced topics in computer architecture. Fourth year UVa undergraduate students interested to enroll should meet a minimum prerequisite requirement of an A- in the undergraduate computer architecture course CS 3330 or equivalent. Graduate students who focus on other complimentary CS disciplines are encouraged to enroll, but are expected to pick up relevant architecture background as we progress through the course. This course will satisfy breadth requirements under the "Computer Systems" category.

Useful resources to pick up architecture background:

• Appendices A, B, and C of the required textbook (Note: we will briefly cover the material in Appendix C).
• Undergraduate textbook: Patterson and Hennessy, "Computer Organization and Design: the Hardware/Software Interface"

Grading

The grading breakdown for this course is:

• 5%: Class/Piazza participation
• 5%: Peer Review
• 15%: 3 homework assignments (including HW0)
• 15%: Value Prediction Championship (Sep 26 - Oct 26)
• 15%: In-class hacking workshop (Nov 9-16)
• 25%: SoK study on cross-cutting themes in Computer Architecture (Due Dec 9)
• 20%: Final exam (on Dec 15 at 2 pm in class)

We will NOT use an absolute grading scale for this course. Your final letter grades will be assigned based on your overall performance, relative to the class average. In addition, you will receive an automatic level-up in your letter grade (e.g., A- to A) if you ace the final.

Assignments

There will be 3 homework assignments, a value prediction championship, and one SoK (Systematization of Knowledge) study (due Dec 1). Each homework assignment will involve 3-5 exercise problems from the textbook. Links to assignments:

• HW0 -- Background Preparation [LaTeX version] [Solutions]
• HW1 -- Quantitative Analysis and Superscalars [LaTeX version] [Solutions]
• HW2 -- Advanced Processors and Caches [LaTeX version] [Solutions]

Guidelines and Policies:

• You may work in pairs for all homework assignments and the value prediction championship. You may in groups of 3-4 students for the SoK study and the hacking workshop.
• All students in a group will receive the same grade. In addition, each individual member will be given a chance to evaluate other members of the group for every assignment (worth 5% of the overall grade).
• All assignments are to be turned in electronically on Gradescope, at the beginning of the lecture, unless otherwise noted.
• You are strongly encouraged to typeset your assignments, but not strictly required.
• Homework assignments are primarily intended for practice, rather than assessment. No single problem will have a significant impact on your final grade.
• Late assignments are not encouraged. An assignment that is turned in before solutions are posted will be assessed a flat 10% (of the maximum score) late penalty. If you turn in the assignment after the solutions have been posted, a flat 20% (of the maximum score) penalty will be applied.

Schedule

Date	Topic	Assignment
Aug 24	Introduction, Motivation, and Course Logistics	HW0 and SoK topics out
Aug 29	Quantitative Analysis in Computer Architecture Reading: H&P Chapter 1.9 Amdahl's Law in the Multicore Era, IEEE Computer, 2008	-
Aug 31	Technology Scaling and Dark Silicon Reading: Dark silicon and the end of multicore scaling, ISCA 2009	-
Sep 5	Labor Day	-
Sep 7	Instruction Set Architecture Reading: Harnessing ISA Diversity: Design of a Heterogeneous-ISA Chip Multiprocessor, ISCA 2014 The Impact of ISAs on Performance, ISCA Workshop on Duplicating, Deconstructing, and Debunking, 2017	HW0 due
Sep 12	Pipelined Datapath and Control Reading: H&P Appendix C	HW1 out
Sep 14	Pipelining: Data and Control Hazards Reading: Chapter 3.1	-
Sep 19	Branch Prediction Reading: H&P Chapter 3.3 A study of branch prediction strategies, ISCA 1981	-
Sep 21	Intel FoMR PI Meeting	-
Sep 26	More Speculative Execution and Spectre Reading: H&P Chapter 3.9 Spectre Attacks: Exploiting Speculative Execution, IEEE S&P 2019	Value Prediction Championship begins
Sep 28	Exposing and Exploiting ILP-1 Reading: Introducing the IA-64 Architecture, IEEE Micro 2000 The Design of the Microarchitecture of UltraSPARC-I, IEEE 1995 H&P Chapters 3.2 and 3.7	-
Oct 3	Fall Reading Day	-
Oct 5	MICRO 2022	-
Oct 10	Exposing and Exploiting ILP-2 Reading: Introducing the IA-64 Architecture, IEEE Micro 2000 The Design of the Microarchitecture of UltraSPARC-I, IEEE 1995 H&P Chapters 3.4-3.5	-
Oct 12	OOO Processors -- Scoreboarding and Tomasulo's Algorithm Reading: H&P Chapters 3.6 and 3.8	-
Oct 17	OOO Processors with Explicit Register Renaming Reading: The MIPS R10000 Superscalar Microprocessor, IEEE Micro 1996	HW1 due
Oct 19	Multithreading Architectures Reading: Chapter 2 from Multithreading Architecture, Synthesis Lectures on Computer Architecture Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor, ISCA 1996	-
Oct 24	Case Study: Intel Sandybridge, Haswell, and Skylake Reading: The Case for a Single-Chip Multiprocessor, ASPLOS 1996 Chapters 2.4, 2.3, 2.2, and 2.7 from Intel® 64 and IA-32 Architectures Optimization Reference Manual in that order.	-
Oct 26	Heterogeneous Chip Multiprocessors Reading: Single-ISA Heterogeneous Multi-Core Architectures: The Potential for Processor Power Reduction, MICRO 2003 Composite-ISA Cores: Enabling Multi-ISA Heterogeneity Using a Single ISA, HPCA 2019 Chapter 2.1 from Intel® 64 and IA-32 Architectures Optimization Reference Manual (latest version)	Value Prediction Championship ends, HW2 out
Oct 31	Cache Design and Performance Reading: A Case for Direct-Mapped Caches, IEEE Computer, 1988	-
Nov 2	Cache Optimizations Reading: Improving Direct-Mapped Cache Performance by the Addition of a Small Fully-Associative Cache and Prefetch Buffers, ISCA 1990 Chapters 2 and 3 of A Primer on Hardware Prefetching, Synthesis Lectures on Computer Architecture	-
Nov 7	Side-Channel Attacks Reading: Chapters 8.1-8.4 from Principles of Secure Processor Architecture Design Covert and Side Channels due to Processor Architecture, ACSAC 2006 Last-Level Cache Side-Channel Attacks are Practical, IEEE S&P 2015	-
Nov 9	In-Class Hacking Workshop: Day-1 Important Links: Starter Code Computing Resources and SSH access	-
Nov 14	No Class (under lockdown)	-
Nov 16	In-Class Hacking Workshop: Day-2	-
Nov 21	Final Review Important Links: Practice Problems Solutions	-
Nov 23	Thanksgiving Break	-
Nov 28	SoK Presentations Day-1 Presentations: Side-Channel Attacks: Anne Zhang, Youwei Chang, Kane Aldrich Heterogeneous Computing: Keshara Tikiri Bandara Weerasinghe, Uday Kiran, Derek Edward Johnson Architectural Support for Quantum Computing: Qichang Liu, John Shen	HW2 due
Nov 30	SoK Presentations Day-2 Presentations: Hardware Specialization for AI/ML: Khyati Kiyawat, Alenkruth Krishnan Murali, Sabiha Tajdari Side-Channel Attacks: Edward Yen-Ting Lue, Chase Hildebrand Hardware Specialization for AI/ML: Xiamei Zhang, Qinglin Li, Zihui Jin, Blake X. Wang Hardware Specialization for AI/ML: Zhuoyang Zhang, Bingxue Xie, Xiangfu Li, Hongyu Xiang	-
Dec 5	SoK presentations: Day-3 Presentations: Side-Channel Attacks: Saket Upadhyay, Yilong Yang, Joseph Peter Loggi Hardware Specialization for AI/ML: Ye Sun, Ziao Yu, Simeng Hao, Yifan Zhang Hardware Specialization for AI/ML: Viswajith Govinda Rajan, Xinyue Fan, Ashish Anil Gawali Hardware Specialization for AI/ML: Hongying Dong, Yizhe Zhang, Xueren Ge, Jingping Wan	-

Honor Code

I trust every student in this course to fully abide by the University's Honor Code and pledge to not commit academic fraud. You are allowed to discuss, collaborate, and brainstorm both within and outside your group. However, you're not allowed to plagiarize solutions/text from another student's assignment or from the internet. Cheating will be taken seriously and will be reported to the honor committee. All suspected honor violations will receive an immediate zero on that assignment regardless of any action taken by the Honor Committee.

Please let me know if you have any questions regarding the course Honor policy. If you believe you may have committed an Honor Offense, you may wish to file a Conscientious Retraction by calling the Honor Offices at (434) 924-7602. For your retraction to be considered valid, it must, among other things, be filed with the Honor Committee before you are aware that the act in question has come under suspicion by anyone. More information can be found here. Your Honor representatives can be found at this link

Learning Accommodations

Students with disabilities or learning needs
It is my goal to create a learning experience that is as accessible as possible. If you anticipate any issues related to the format, materials, or requirements of this course, please meet with me outside of class so we can explore potential options. Students with disabilities may also wish to work with the Student Disability Access Center to discuss a range of options to removing barriers in this course, including official accommodations. Please visit their website for information on this process and to apply for services online. If you have already been approved for accommodations through SDAC, please send me your accommodation letter and meet with me so we can develop an implementation plan together.

Discrimination and power-based violence
The University of Virginia is dedicated to providing a safe and equitable learning environment for all students. To that end, it is vital that you know two values that I and the University hold as critically important:

1. Power-based personal violence will not be tolerated.
2. Everyone has a responsibility to do their part to maintain a safe community on Grounds.

If you or someone you know has been affected by power-based personal violence, more information can be found on the UVA Sexual Violence website that describes reporting options and resources available.

As your professor and as a person, know that I care about you and your well-being and stand ready to provide support and resources as I can. As a faculty member, I am a responsible employee, which means that I am required by University policy and federal law to report what you tell me to the University's Title IX Coordinator. The Title IX Coordinator's job is to ensure that the reporting student receives the resources and support that they need, while also reviewing the information presented to determine whether further action is necessary to ensure survivor safety and the safety of the University community. If you wish to report something that you have seen, you can do so at the Just Report It portal. The worst possible situation would be for you or your friend to remain silent when there are so many here willing and able to help.

Religious accommodations
It is the University's long-standing policy and practice to reasonably accommodate students so that they do not experience an adverse academic consequence when sincerely held religious beliefs or observances conflict with academic requirements. Students who wish to request academic accommodation for a religious observance should submit their request in writing directly to me as far in advance as possible. Students who have questions or concerns about academic accommodations for religious observance or religious beliefs may contact the University’s Office for Equal Opportunity and Civil Rights (EOCR) at UVAEOCR@virginia.edu or (434) 924-3200.