Final

You may use any resource that existed prior to this exam opening, including websites, books, etc; but should not consult friends, tutors, forums, or other interactive help for this exam.

You must not share any information about this exam (even how you felt about it) with any party (even others who have taken it) until after it closes at 2020-05-07 23:59 EDT.

The following ask about adding limitations to computer functionality.

Question 1 (dropped) (see above)

Suppose we want to limit the use of the xorq command to only certain users or operation modes. This would require modification of

the operating system code
the processor hardware

Question 2 (see above)

Suppose we want to limit all user-mode programs so they can only access to files have an even number of letters in their names. This would require modification of

the operating system code
the processor hardware

Question 3 (see above)

Suppose we want to throttle bandwidth so each user could only send 1MB of network traffic per minute. This would require modification of

the operating system code
the processor hardware

The following ask about interrupts and related concepts

Question 4 (see above)

What's the difference between an interrupt number and a system call number?

all interrupts use the same system call number
all system calls use the same interrupt number
one communicates hardware to software, the other the other way around
one is received by the OS, the other by user code
they are two names for the same thing

Question 5 (see above)

The following are all true of interrupts; which are also true of signals?

Handling them causes a change in user-vs-kernel permission mode
They are handled by the OS
They can happen between any pair of instructions
They have an identifying number
They originate in hardware

We have often noted each of the following things about memory this semester; these questions ask how they have been refined by our understanding of virtual memory

Question 6 (see above)

Linux on x86-64 splits memory in half: the lower half is user-mode and the upper half is kernel-mode

This is true of both virtual and physical memory
This is true of physical memory
This is true of virtual memory

Question 7 (see above)

The call stack (the one handled by pushq, callq, etc) grows toward smaller addresses

This is true of both virtual and physical memory
This is true of physical memory
This is true of virtual memory

Question 8 (dropped) (see above)

When a process is suspended, allowing other processes to use the processor, its memory is inaccessibly.

This is true of both virtual and physical memory
This is true of physical memory
This is true of virtual memory

Consider the 4-level page table hierarchy we discussed Intel processors using, with a 4K pages, 48-bit virtual addresses, and 52-bit physical addresses

Question 9 (see above)

If I run movq (%rax), %rbx when (%rax) is on a page that is not in the TLB, how many memory accesses does the instruction perform? Answer as a base-10 integer, like "1" or "39"

Answer:

Question 10 (see above)

If I run movq (%rax), %rbx when (%rax) is on a page that is in the TLB, how many memory accesses does the instruction perform? Answer as a base-10 integer, like "1" or "39"

Answer:

Question 11 (see above)

If my code accesses the 50-bit address 0x2100010001000

it acts like I accessed the 45-bit address 0x100010001000 instead
it causes a fault
it works just like accessing any other address

Question 12

If a disk read is performed via Direct Memory Access (DMA),

certain ranges of virutal addresses are handled by the disk instead of by RAM
the disk's write interrupts are routed to RAM directly without user process intervention
the disk modifies the data in a range of physical addresses without processor involvement

The following ask about the ability of devices on a bus to interact. In particular, assume that a bus-topology network connects the keyboard, disk, network card, and processor.

Assume that any special status a bus-connected component can have (hub position, master status, etc) is held by the processor and not the other components.

Question 13 (see above)

Suppose I create a nefarious disk that is programmed to log every keystroke you make. Assume I put any computing power needed for this task inside the disk hardware.

The disk could log keystrokes with no special permissions, but the processor could see it happen.
The disk could log keystrokes with no special permissions and without the processor knowing about it.
This disk would need to get permission from the keyboard first, but could then do the logging itself.
This disk would need to get permission from the processor first, but could then do the logging itself.
This disk would need to have the processor route the keystroke data to the disk.

Question 14 (dropped) (see above)

Suppose I create a nefarious disk that is programmed to send your files to me over your Internet connection. Assume I put any computing power needed for this task inside the disk hardware, but do not have network connectivity in the disk itself.

The disk could send the request to send the files to the network card directly, but the processor could see it happen.
The disk could send the request to send the files to the network card directly, without the processor knowing about it.
This disk would need to get permission from the network card first, but could then send the data to the network card itself.
This disk would need to get permission from the processor first, but could then send the data to the network card itself.
This disk would need to have the processor route the data to the network card.

HTTPS delivered web requests and replies using TLS, TCP, and IP. The TLS encrypts the request and reply body, but does not encrypt the IP and TCP headers.

Question 15 (see above)

Why does TLS not encrypt the IP header?

If it did, the message could be delivered but routing computers could not optmize message flow.
If it did, the message could not be delivered and decrypted at the other end.
If it did, the message could sometimes be delievered but could not detect and/or recover from delivery errors.
None of the above; this was just a choice, not a design necessity.

Question 16 (see above)

Why does TLS not encrypt the TCP header?

If it did, the message could be delivered but routing computers could not optmize message flow.
If it did, the message could not be delivered and decrypted at the other end.
If it did, the message could sometimes be delievered but could not detect and/or recover from delivery errors.
None of the above; this was just a choice, not a design necessity.

The following ask about digital signatures

Question 17 (see above)

Which of the following is used to sign a document?

the recipient's private key
the recipient's public key
the signer's and recipient's shared symmetric key
the signer's private key
the signer's public key

Question 18 (see above)

Which of the following is used to verify the signature of a document?

the recipient's private key
the recipient's public key
the signer's and recipient's shared symmetric key
the signer's private key
the signer's public key

Question 19 (see above)

A digital certificate is

any document with an attached signature
the key to checking an agent you don't trust's signatures, signed by an agent you do trust
the key to checking an agent you do trust's signatures, signed by an agent you don't trust
the key to sending an agent you don't trust your signatures, signed by an agent you do trust
the key to sending an agent you do trust your signatures, signed by an agent you don't trust

The following ask about caches, in particular the memory cache hierarchy

Question 20 (see above)

Why do caches have larger blocks that a single access will need?

to distribute memory bandwidth over time
to limit cache lookup processing time
to optimize repeated writes to the same address
to optimize spatially-local accesses
to optimize temporally-local accesses
to reduce miss rate

Question 21 (see above)

Why do caches have multiple lines per set?

to distribute memory bandwidth over time
to limit cache lookup processing time
to optimize repeated writes to the same address
to optimize spatially-local accesses
to optimize temporally-local accesses
to reduce miss rate

Question 22 (see above)

Why do caches have multiple small sets instead of one large one?

to distribute memory bandwidth over time
to limit cache lookup processing time
to optimize repeated writes to the same address
to optimize spatially-local accesses
to optimize temporally-local accesses
to reduce miss rate

Question 23 (0.5 points) (see above)

Why are some caches write-back?

to distribute memory bandwidth over time
to limit cache lookup processing time
to optimize repeated writes to the same address
to optimize spatially-local accesses
to optimize temporally-local accesses
to reduce miss rate

Question 24 (0.5 points) (see above)

Why are some caches write-through?

to distribute memory bandwidth over time
to limit cache lookup processing time
to optimize repeated writes to the same address
to optimize spatially-local accesses
to optimize temporally-local accesses
to reduce miss rate

Question 25

Which of the following best describes Amdahl's Law?

Adding parallelism is the main way hardware becomes faster.
Speeding up part of a task doesn't make the other parts faster.
The number of transistors on a chip doubles every few years.
Throughput it more important than latency for real workloads.
With enough parallelism, any timing goal can be met.

Question 26

Which two of the following correctly describe concurrency and parallelism?

If concurrent, then parallel.
If not concurrent, then not parallel.
If not parallel, then not concurrent.
If parallel, then concurrent.

Question 27

Which of the following are true of synchronization primitives?

Barriers are commonly used to create mutual exclusion.
Monitors are commonly used to create mutual exclusion.
One mutex can do everything one reader-writer lock can do.
One reader-writer lock can do everything one mutex can do.

Most synchronization primitives can be created using several other primitives and a few auxiliary data structures. Which of the following is closest to implementing barriers with other pthreads primitives?

Question 28 (see above)

The pthread_barrier_t needs a condition variable for threads to wait on, a mutex to lock access to other variables, and which of the following?

a Boolean to show if the barrier may be passed
a counter to show how many threads are waiting
a counter to show how many threads this barrier requires before continuing
a list of thread IDs allowed to use the barrier
a list of thread IDs waiting on the barrier

Question 29 (see above)

If our pthread_barrier_t was implemented as

lock the mutex
manipulate variables
if (variables suggest should wait) {
    wait on condition variable
} else {
    release all waiting threads
}
unlock the mutex

what would go wrong? Assume the barrier requires at least two threads to continue.

This has a race condition that could not result in a deadlock
This has a race condition that could result in a deadlock
This has a race condition that could result in one thread waiting too long
This would always deadlock

Question 30 (see above)

If our pthread_barrier_t was implemented as

lock the mutex
manipulate variables
if (variables suggest should wait) {
    unlock the mutex
    wait on condition variable
} else {
    unlock the mutex
    release all waiting threads
}

what would go wrong? Assume the barrier requires at least two threads to continue.

This has a race condition that could not result in a deadlock
This has a race condition that could result in a deadlock
This has a race condition that could result in one thread waiting too long
This would always deadlock

The following ask about Dining Philosophers and its solutions documented in Lab 09.

Question 31 (see above)

The "arbitrator" solution to dining philosophers ensures there is no deadlock by removing which of the necessary conditions of deadlock?

Question 32 (see above)

The "resource hirearchy" solution to dining philosophers ensures there is no deadlock by removing which of the necessary conditions of deadlock?

Question 33

Pipelining ____ throughput and ____ latency.

Pipelining decreases throughput and decreases latency.
Pipelining decreases throughput and increases latency.
Pipelining increases throughput and decreases latency.
Pipelining increases throughput and increases latency.

Question 34

Out of order execution ____ throughput and ____ latency.

Out of order execution decreases throughput and decreases latency.
Out of order execution decreases throughput and increases latency.
Out of order execution increases throughput and decreases latency.
Out of order execution increases throughput and increases latency.

Question 35

Speculative execution can increase the performance of

out-of-order processors
pipelined in-order processors
single-sage processors, like we discussed in COA1

Both Spectre and Meltdown exploits included (a compiled or language-specifc version of) the code

y = arr[(*x) * 4096]

where x was a pointer to an address that should not be accessible, but whose value was leaked by the exploit; arr was a pointer to memory owned by the attacker; and y was a register owned by the attacker.

Question 36 (see above)

After running the above code, how do these exploits learn the contents of *x?

By checking the cache presence of *x
By checking the cache presence of arr[0], arr[4096], arr[8192], ..., arr[255*4096]
By checking the cache presence of y
By checking the contents of arr[0], arr[4096], arr[8192], ..., arr[255*4096]
By checking the contents of y
By checking the page table entry for *x
By checking the page table entry for arr[0], arr[4096], arr[8192], ..., arr[255*4096]
By checking the page table entry for y

Question 37 (see above)

Why the 4096 multiplicand?

So each value has a different cache line
So each value has a different page table entry
To cause 1-byte-integer overflow for all values of *x
To cause 2-byte-integer overflow for some but not all values of *x
To prevent speculative caching via prefetching
To prevent speculative execution via prediction

Return to course page Return to index normal