How are C and C++ related? Reset Selection

Some of the tools we use in this class use strict ANSI-compliant C. You can get this version by running "gcc -ansi -pedantic-errors" or "clang -ansi -pedantic-errors". In this standard one (and only one) of the following is an error. Which one?

Reset Selection

Suppose you have a variable declared as an array (e.g., "int y[32]") and another declared as a pointer (e.g., "int *z"). In what way do the two variable differ? Reset Selection

If we declare "int *x = malloc(16);" how many ints can fit inside x? Reset Selection

Suppose a process spends 1 second doing task A, then 3 doing B, then 6 doing C. Which of the following will give the biggest speedup? Reset Selection

Given some type T (where sizeof(T) ≠ 1) and a variable declared "T *x", which of the following is equivalent to "x[3]"? Reset Selection

Suppose I have a type declared "typedef struct range_t { int length; int *ptr; } range;" and a function declared "range foo()" that returns a range with length=8 and an 8-element heap-allocated array pointed to by ptr. How much heap memory does foo need to use? Select all that apply (i.e., the answer should be the sum of the options you pick).

A. 32 bytes for the array
B. 4 bytes for the length
C. 8 bytes for the pointer (assuming this is a 64-bit machine)
D. space for foo's activation record
E. more memory not listed above

How much memory is used to represent the string "3330" in C? Answer as an integer number of bytes (expressed in the usual base-10 format with no leading zeros). Ignore alignment and other nuances of memory that we have not discussed.

Question 1 of 4 1.0 Points Suppose we have a signed char x. What is the numeric value stored in x after executing "x = -1; x >>= 1;"? A. -1 B. 0 C. 127 D. -2 E. none of the above Reset Selection

Question 2 of 4 1.0 Points Suppose we have an unsigned char x. What is the numeric value stored in x after executing "x = -1; x >>= 1;"? A. -1 B. 0 C. 127 D. -2 E. none of the above Reset Selection

Question 3 of 4 1.0 Points When doing arithmetic by hand in binary, which of the following binary operations are different for signed vs unsigned values? Assume (as all hardware I know of assumes) that the signed values are in 2's compliment form. A. - B. + and - C. / D. * and / E. all of the above F. none of the above Reset Selection

Question 4 of 4 1.0 Points If we had a 3-byte (24-bit) floating point number with 18 exponent bits, how many of the 224 possible values of the floats would be NaN values? Answer with a non-negative integer written in base 10 with no leading zeros.

Question 1 of 4 1.0 Points In ATT-format assembly (the default for gnu tools and our textbook), registers are prefixed by a % A. always B. if used directly, but not in memory access notation C. never Reset Selection

Question 2 of 4 1.0 Points In ATT-format assembly (the default for gnu tools and our textbook), numerical immediate values are prefixed by a $ A. always B. if used directly, but not in memory access notation C. never Reset Selection

Question 3 of 4 1.0 Points While can be converted to assembly either as jump-to-middle or as guarded-do, the latter of which the book describes as enabling other optimizations. Without those extra optimizations, which one involves executing more instructions? A. jump-to-middle involves more executed instructions B. guarded-do involves more executed instructions C. they involve the same number of executed instructions Reset Selection

Question 4 of 4 1.0 Points The text discusses stack usage with call and ret, but this is mostly convention, not forced behavior. Which of the following jumps to an address stored in a register? A. push %rax; call L; L: nop B. ret; pop %rax C. push %rax; ret D. call L; L: pop %rax Reset Selection

Question 1 of 4 1.0 Points Y86-64 is little-endian. What sequence of bytes would represent irmovq $0x1234, %r8? Answers are listed in hex A. 43 21 00 00 00 00 00 00 8f 03 B. 03 8f 43 21 00 00 00 00 00 00 C. 30 f8 00 00 00 00 00 00 12 34 D. 34 12 00 00 00 00 00 00 f8 30 E. 30 f8 34 12 00 00 00 00 00 00 Reset Selection

Question 2 of 4 1.0 Points Compare an rrmovq and a cmovXX with an unconditional fn A. they are the same in encoding and meaning B. they are the same in encoding but not in meaning C. they are the same in meaning but not in encoding D. they differ in both encoding and meaning Reset Selection

Question 3 of 4 1.0 Points Which of the following operand formats from x86 also exist in Y86? Select all that apply A. 42(%rax) B. 42(%rax, %rcx) C. (%rax) D. $42 E. 42(%rax, %rcx, 4) F. %rax G. 42

Question 4 of 4 1.0 Points Figure 4.2 does not include the encoding for a label. This is because A. labels can be implemented using other instructions B. labels exist but don't encode to instructions C. there are no labels in Y86 D. the figure is incomplete Reset Selection

While can be converted to assembly either as jump-to-middle or as guarded-do, the latter of which the book describes as enabling other optimizations. Without those extra optimizations, which one involves executing more instructions? Reset Selection

The text discusses stack usage with call and ret, but this is mostly convention, not forced behavior. Which of the following jumps to an address that is stored in a register? Reset Selection

Y86-64 has the following features. Select all that suggest Y86-64 is a RISC architecture:

A. 26 instructions (counting all the flavors of jXX, etc)
B. Each instruction does one thing (one move, one simple math operation, etc)
C. Instruction sizes may be 1, 2, 9, or 10 bytes
D. Exactly three address formats: 42, 42(%rax), and (%rax).
E. OPq only accepts register operands
F. Any assembly operation may follow any other
G. Condition Codes

In a little-endian machine, select all that apply:

A. The low-order byte of an integer is placed at a smaller address than the high-order byte of that same integer
B. For an array x, x[1] is placed at a smaller address than x[0]
C. For a struct { int x; int y; }, y is placed at a smaller address than x

Question 1 of 5 1.0 Points irmovq and pushq both have a register byte (rA:rB ← M1[PC+1]) but each only use one of the two registers: irmovq only uses rB and pushq only uses rA. ipushq should A. have a register byte and use both rA and rB B. have a register byte and only use rA C. have a register byte and only use rB D. not have a register byte Reset Selection

Question 2 of 5 1.0 Points irmovq does nothing in the decode stage; pushq does two things there (both valA ← R[rA] and valB ← R[%rsp]). What should be in ipushq's decode stage? A. both valA ← R[rA] and valB ← R[%rsp] (like pushq) B. just valA ← R[rA] C. just valB ← R[%rsp] D. nothing (like irmovq) Reset Selection

Question 3 of 5 1.0 Points irmovq's execute stage simply renames valC as valE (valE ← 0 + valC). The book has this renaming step because later in the chapter, when they turn these descriptions into actual muxes and wires, there isn't a wire named valC in the writeback stage. pushq's execute stage does some computation (valE ← valB + (−8)). ipushq's execute stage should: A. keep valC around for later use in writeback (like irmovq) B. compute "something + (−8)" (like irmovq) C. both of the above D. neither of the above Reset Selection

Question 4 of 5 1.0 Points irmovq does nothing during the memory stage; pushq writes the value it read from a register (valA) into memory (M8[valE] ← valA). ipushq's memory stage should A. do nothing (like irmovq) B. write a value from a program register into memory (like pushq) C. write a value into memory, but not a value from a program register (other instructions do this; e.g. call) D. read a value from memory (other instructions do this; e.g. mrmovq) Reset Selection

Question 5 of 5 1.0 Points irmovq's writeback is (R[rB] ← valE); pushq's writeback is (R[%rsp] ← valE). ipushq's writeback should be: A. R[rB] ← valE B. R[%rsp] ← valE C. R[rB] ← something other than valE D. R[%rsp] ← something other than valE E. both (R[rB] ← something) and (R[%rsp] ← something) F. do nothing Reset Selection

Section 4.3.3 "SEQ Timing" emphasizes that (1) no stage depends on the results of a later stage and (2) no instruction reads a register or memory value after writing it. Which of the following would violate one of these two rules? Reset Selection

irmovq moves from an immediate value (which can be found in valC) to the register file, but neither figure 4.23 nor the up-close view of memory in figure 4.28 has an arrow from valC to the register file. Why not? Reset Selection

Question 1 of 7 1.0 Points The main reason we add pipelining is to A. increase latency B. decrease latency C. increase throughput D. decrease throughput E. increase the versatility of the processor F. decrease the complexity of the processor Reset Selection

Question 2 of 7 1.0 Points Suppose three people are making pies. A makes the crust and hands it to B, who adds the filling and hands it to C, who bakes it. If the three live in separate states and send their partially-completed pies via post, they all have a lot of down-time waiting for the pies to arrive. This inefficiency is called A. Nonuniform partitioning B. Diminishing returns of deep pipelining C. Neither of the above Reset Selection

Question 3 of 7 1.0 Points Suppose 26 people are making pies. A gets a bowl, B adds flour to it, C adds oil, D mixes, E gathers into a ball, ... Y removes it from the oven, and Z puts it in a box. Each one's task is so small that they spend more time moving back and forth than they do actually working. This inefficiency is called A. Nonuniform partitioning B. Diminishing returns of deep pipelining C. Neither of the above Reset Selection

Question 4 of 7 1.0 Points Suppose three people are making pies. A makes the crust and hands it to B, who adds the filling and hands it to C, who bakes it. If B requires twice as much time per pie as A and C, then A and C have a lot of down-time waiting for B. This inefficiency is called A. Nonuniform partitioning B. Diminishing returns of deep pipelining C. Neither of the above Reset Selection

Question 5 of 7 1.0 Points Generic registers only change output values on a rising clock edge. Which of the following can change the output of a pipeline register before a rising clock edge? Select all that apply. A. bubble goes from 0 to 1 B. stall goes from 0 to 1 C. bubble goes from 1 to 0 D. stall goes from 1 to 0 E. input changes while bubble and stall are both 0 F. input changes while bubble is 1 G. input changes while stall is 1 H. none of the above Reset Selection

Question 6 of 7 1.0 Points The bubble input should be used to implement pipeline control in what way? (The trinary operator "?:" below has the same semantics it has in C.) A. G.clock = bubble ? 0 : G.clock B. G.input = bubble ? 0 : G.input C. output = bubble ? 0 : G.output D. none of the above Reset Selection

Question 7 of 7 1.0 Points The stall input should be used to implement pipeline control in what way? (The trinary operator "?:" below has the same semantics it has in C.) A. G.clock = stall ? 0 : G.clock B. G.input = stall ? 0 : G.input C. output = stall ? 0 : G.output D. none of the above Reset Selection

In the context of chapter 4, a hazard is a characteristic of which of the following? Reset Selection

In the context of chapter 4, a dependency is a characteristic of which of the following? Reset Selection

Suppose we are executing a program containing instructions: i1, i2, i3, i4, ... etc. Assume all of the instructions run in order and without jumps, stalls, dependencies, or hazards.  Assume the five-stage pipeline discussed in the textbook.

If i5 is in the execute (E) stage, what is in memory (M)?

Reset Selection

Suppose we are executing a program containing instructions: i1, i2, i3, i4, ... etc. Assume all of the instructions run in order and without jumps or stalls. Assume the five-stage pipeline discussed in the textbook.

If we use data forwarding to get i5 through the execute (E) stage, we did which of the following?

Reset Selection

Suppose we are executing a program containing instructions: i1, i2, i3, i4, ... etc. Assume all of the instructions run in order and without jumps or forwarding. Assume the five-stage pipeline discussed in the textbook.

If we use stalling to get i5 through the execute (E) stage, we did which of the following?

Reset Selection

If power is lost for 1 millisecond and then restored, which kind of RAM will still have its contents? Reset Selection

Which of the following has the best temporal locality? Consider only data accesses, not instructions. Reset Selection

Which of the following has the best spatial locality? Consider only data accesses, not instructions. Reset Selection

"Cache" rhymes with Reset Selection

Which of the following is blamed on the cache's replacement policy? Reset Selection

Dirty bits are associated with Reset Selection

Given a byte-addressable memory with a 4GB address space; and a direct-mapped cache with 64-byte blocks and 16-bit tags; how many lines are there in the cache? Answer as a base-10 integer with no leading 0:

Suppose two set-associative caches (A and B) have the same total data capacity, same address size, and same block size, but cache A has twice as many lines per set as cache B. Which of the following is true? Reset Selection

In a set-associative cache, which of the following does *not* impact the way an address is split into tag, index, and offset? Reset Selection

For each code snippet below, assume that p and q each points to an array containing the first nine prime numbers (2, 3, …, 23). Select the answer(s) if and only if the code behaves the same both when p and q are aliases and when they are not aliases.

A. for(i=0; i<9; i+=1) p[i] = q[n-i-1];
B. i=0; while(p[q[i]] < 10) i += 1;
C. int tmp = *p; *p = *q; *q = tmp;
D. *p ^= *q; *q ^= *p; *p ^= *q;

Which of the following best describes the intent of "eliminating loop inefficiencies"? Reset Selection

Function inlining (described in an aside in section 5.1) is the ultimate solution to reducing procedure calls. In non-recursive code, it is possible to inline *all* procedures and have no procedure call overhead at all. Doing this is a bad idea because (select all that apply)

A. It decreases the ability to re-use variables and/or registers
B. It makes your code long and hard to maintain
C. It results in a loss of temporal locality of code
D. None of the above

Which of the following does NOT appear to have an unneeded memory reference? Assume the program does some work between the two address accesses. Reset Selection

Loop unrolling principally reduces what performance cost? Reset Selection

"Multiple Accumulators" is listed under "Parallelism," meaning "pipeline parallelism." They help because Reset Selection

Which of the following will be fastest? Reset Selection

Register spilling is a bigger problem if Reset Selection

Branch misprediction is a bigger problem if Reset Selection

Profilers are particularly useful if Reset Selection

Question 1 of 8 1.0 Points All of the following are true for either Java or Hardware exceptions, and most are true of both; which one is only true of one of the two? A. The handlers are outside the normal flow of execution rules B. The handler can discover where the exception occurred C. The code that caused the exception can be resumed after handling D. The handlers are written in software E. The handler does not have to resolve the exception Reset Selection

Question 2 of 8 0.5 Points Exception handler A. ArithmeticException B. catch block C. Java terminates with a stack trace D. KeyEvent E. many catches for one try F. subclass of Exception G. throw statement Reset Selection

Question 3 of 8 0.5 Points Exception number A. ArithmeticException B. catch block C. Java terminates with a stack trace D. KeyEvent E. many catches for one try F. subclass of Exception G. throw statement Reset Selection

Question 4 of 8 0.5 Points Exception table A. ArithmeticException B. catch block C. Java terminates with a stack trace D. KeyEvent E. many catches for one try F. subclass of Exception G. throw statement Reset Selection

Question 5 of 8 0.5 Points Interrupt A. ArithmeticException B. catch block C. Java terminates with a stack trace D. KeyEvent E. many catches for one try F. subclass of Exception G. throw statement Reset Selection

Question 6 of 8 0.5 Points Trap A. ArithmeticException B. catch block C. Java terminates with a stack trace D. KeyEvent E. many catches for one try F. subclass of Exception G. throw statement Reset Selection

Question 7 of 8 0.5 Points Fault A. ArithmeticException B. catch block C. Java terminates with a stack trace D. KeyEvent E. many catches for one try F. subclass of Exception G. throw statement Reset Selection

Question 8 of 8 0.5 Points Abort A. ArithmeticException B. catch block C. Java terminates with a stack trace D. KeyEvent E. many catches for one try F. subclass of Exception G. throw statement Reset Selection

Consider two processes A and B. Which of the following is equivalent to the statement "A and B are executing concurrently"? Reset Selection

Consider two processes A and B. Which of the following is equivalent to the statement "A and B are executing in parallel"? Reset Selection

Signals are how Reset Selection

Interrupts are how Reset Selection

Traps are how Reset Selection

Using virtual addresses, Reset Selection

If each PTE is 8 bytes and each page is 4 KB, how large is a single-level page table for 30-bit addresses? Reset Selection

A page table's conceptual datatype (implemented by both single- and multi-level page tables) is Reset Selection

A page table entry in a multi-level page table stores metadata (such as a valid bit) and Reset Selection

To look up an address (not to access the data at the address, just to perform the address translation) using a three-level page table, the MMU needs to access memory Reset Selection

If we extend the book's comparison between caches and page tables, for a 48-bit virtual address with 4 KB pages and 40-bit physical addresses, how many bits long is the tag? Answer as a normal decimal integer:

The set index of an address going to a cache is like the _____ of a virtual address going to a page table Reset Selection

Virtual memory can be thought of as using RAM as a cache for disk. Thought of in this way, virtual memory is Reset Selection

Some page faults generate SIGSEGV (a.k.a. "segfault") and others are handled without any problems. Which of the following can be handled without a SGISEGV?

A. accessing user address space in the page table as the user
B. accessing kernel address space in the page table as the user
C. accessing user address space in the page table as the kernel
D. accessing kernel address space in the page table as the kernel
E. accessing user address space that is not in the page table as the user

 

Anywhere it matters, assume the cache is set-associative and the virtual memory uses multi-level page tables

Question 1 of 7 1.0 Points Requires an exception table to exist A. true of both B. true of caches but not virtual memory C. true of virtual memory but not caches D. true of neither Reset Selection

Question 2 of 7 1.0 Points Code written assuming we have this would still work without it, though it may run more slowly A. true of both B. true of caches but not virtual memory C. true of virtual memory but not caches D. true of neither Reset Selection

Question 3 of 7 1.0 Points Stores contiguous chunks of data in the faster store (to take advantage of spatial locality) A. true of both B. true of caches but not virtual memory C. true of virtual memory but not caches D. true of neither Reset Selection

Question 4 of 7 1.0 Points Enables the enforcement of read-only memory A. true of both B. true of caches but not virtual memory C. true of virtual memory but not caches D. true of neither Reset Selection

Question 5 of 7 1.0 Points Is used for all memory accesses (both in user and kernel mode) A. true of both B. true of caches but not virtual memory C. true of virtual memory but not caches D. true of neither Reset Selection

Question 6 of 7 1.0 Points The same address always maps to the same location in the slower store A. true of both B. true of caches but not virtual memory C. true of virtual memory but not caches D. true of neither Reset Selection

Question 7 of 7 1.0 Points The same address always maps to the same location in the faster store A. true of both B. true of caches but not virtual memory C. true of virtual memory but not caches D. true of neither Reset Selection