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Pre-quiz on fourth week's material. Figure numbers are the same in both 2nd and 3rd edition of the textbook.

The SEQ processor design uses conceptual stages. Sometimes it refers to six of them, and other times it leaves off the sixth (PC Update). We'll usually leave off PC Update, which is why it does not appear as an option below.

Question 1: (see above) Which stage is responsible for retrieving instruction bytes from memory based on the PC?

  1. Fetch

  2. Decode

  3. Execute

  4. Memory

  5. Writeback

Question 2: (see above) Which stage is responsible for interpreting the bytes of an instruction to determine what action is being requested?

  1. Fetch

  2. Decode

  3. Execute

  4. Memory

  5. Writeback

Question 3: Suppose R is a register (like those discussed in the textbook) with input x, clock input c, and output y.

  1. Whenever you change x, the value of y changes to match x

  2. If you change x while c is 1, the value of y changes to match x

  3. If you change x while c is 0, the value of y changes to match x

  4. If you change c to 1 after changing x, the value of y changes to match x

  5. If you change c to 0 after changing x, the value of y changes to match x

Question 4: The HCL [a : b; c : d; 1 : e] is functionally equivalent to

  1. the C expression a ? b : (c ? d : e)

  2. the Python expression [a : b; c : d; 1 : e] (i.e., it declates a Map data structure)

  3. the C statements a = b; c = d; 1 = e;

  4. the C statements b = a; d = c; e = 1;

  5. the C expression a == b || c == d || 1 == e

  6. the C expression a == b && c == d && 1 == e

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