For the following questions, refer to Figure 6.26 in the textbook.
Question 1: (see above) If a cache has 1024 sets, each containing two 128 byte blocks, then what is the number of block offset bits? Answer as a normal base-10 number.
Question 2: (see above) If a cache for a processor with 32-bit physical memory addresses is direct-mapped, has 64 byte blocks, and 20 tag bits in each cache line, then the size of the cache (excluding overhead) is:
Question 3: (see above) If a cache for a processor with 64-bit physical memory addresses has 1024 sets and 2 lines per set, and each line contains a 32 byte block, then what is the number of tag bits in each line of the cache? Answer as a normal base-10 number.
Question 4: Suppose a cache has 20 tag bits, 8 index bits, and 4 block offset bits. In which set would
the memory address 0x12345678 be looked up?
Question 5: Which of the following changes can decrease the number of conflict misses in a cache?
Select all that apply
In the following, assume where possible that the changes listed are independent: that cache size can be changed without modifying block size, etc.
Question 6: (see above) Which of the following changes are likely to increase the hit rate of a cache?
Select all that apply
Question 7: (see above) Which of the following changes are likely to increase the miss penalty of a cache?
Select all that apply
Question 8: (see above) Which of the following changes to the cache are likely to increase how much it can
benefit from spatial locality?
Select all that apply