All quizzes

All quizzes

Quiz 01

Consider the following C snippet:

extern int strcmp(const char *, const char*);

const char *foo(const char *bar) {
    if (!strcmp(bar, "special")) {
        return "value 1";
    } else {
        return "value 2";
    }
}

Suppose this snippet is contained in the file foo.c, which is compiled into an object file foo.o, and then combined with a main.o to produce an executable called main.exe which calls the foo() function whenever it is run.

Question 1 (1 points): (see above) Ignoring information only present for debugging, the string "value 1" is likely to appear in _______.
Select all that apply

  1. foo.o

  2. main.o

  3. main.exe

Question 2 (1 points): (see above) Ignoring information only present for debugging, the name "foo" is likely to appear in ________.
Select all that apply

  1. foo.o

  2. main.o

  3. main.exe

Consider the following assembly function example:

example:
    movq %rdi, %rax
loop:
    subq $10, %rdi
    jg loop
    ret

Recall that in the x86-64 calling convention, the first argument to a function is in the register %rdi and the return value is in %rax.

Question 3 (0 points): (see above) [We are dropping this question due an error discovered after we released the quiz.] Which of the following C snippets is equivalent to this function?

  1. long example(long argument) { do { argument -= 10; } while (argument > 0); return argument; }

  2. long example(long argument) { do { argument -= 10; } while (argument > 10); return argument; }

  3. long example(long argument) { while (--argument > 10) {} return argument; }

  4. long example(long argument) { while (argument > 10) { argument -= 10; } return argument; }

Question 4 (1 points): (see above) When this function returns, what are possible values of the ZF condition code?
Select all that apply

  1. 0

  2. 1

Question 5 (1 points): (see above) When this function returns, what are possible values of the SF condition code?
Select all that apply

  1. 0

  2. 1

Read section 2.1.6-7 of the textbook and answer the following questions.

Question 6 (1 points): (see above) Using bitwise operators, integers can be used to represent sets, where each bit being sets indicates whether an element with a particular index is included in the set. If this is being done in C, if a and b are integers representing sets, then producing a set containing the elements in both a and b (sometimes called "set intersection") can be done with the expression:

  1. a & b

  2. a && b

  3. a | b

  4. a || b

  5. a ^ b

  6. (~a) ^ (~b)

Read section 4-4.1.3 of the textbook and answer the following questions.

Question 7 (1 points): (see above) An instruction set architecture (ISA) determines
Select all that apply

  1. what machine code that would be produced by a compiler looks like

  2. what circuits that would be produced by a processor designer look like

  3. what lower-level programming languages like C look like

  4. how long instructions take to execute

Question 8 (1 points): (see above) In section 4.1.3, the textbook explains how rmmovq %rsp, 0x123456789abcd(%rdx) is encoded as 40 42 cd ab 89 67 45 23 01 00. If we were to instead encode irmovq $0x123456789abcd, %rsp, what would its encoding be?

  1. 30 42 cd ab 89 67 45 23 01 00

  2. 30 f2 cd ab 89 67 45 23 01 00

  3. 32 cd ab 89 67 45 23 01 00

  4. 40 f2 cd ab 89 67 45 23 01 00

  5. 30 f2 00 01 23 45 67 89 ab cd

  6. none of the above

Quiz 02

Question 1 (1 points): Which of the following C expressions are always true, assuming x and y are 32-bit unsigned ints between 0 and 9999999, inclusive?
Select all that apply

  1. ((x << 8) & 0xFF) == (y ^ (y & 0xFF))

  2. (x ^ y) < (x | y)

  3. (((x << 4) | ((y >> 4) & 0xF)) & 0xFF) == (((x & 0xF) << 4) | ((y & 0xFF) >> 4))

  4. ((((x & 0xF) >> 4) | ((y & 0xFF) >> 4)) | x) == (((x >> 4) | x) | ((y >> 4)& 0xF))

Question 2 (1 points): Consider the following incomplete C function:

unsigned int copy_lsb(unsigned int x) {

    CODE HERE

}

Which of the following could replace CODE HERE to make this function return a 32-bit unsigned int where each byte is a copy of the least significnat byte of the argument x?
Select all that apply

  1. return x | (x << 8) | (x << 16) | (x << 24); }

  2. return (x & 0xFF) | ((x & 0xFF) << 8) | ((x & 0xFF) << 16) | ((x & 0xFF) << 24);

  3. unsigned int y = x & 0xFF; y = y | (y << 16); return y | (y << 8);

  4. unsigned int y = x; y = (y << 8) & 0xFF; return (y << 16) & 0xFF;

Consider the following C snippet:

int array[4] = {0x1234, 0x5678, 0xABCD, 0xEF01};

Suppose on a system with 32-bit, little-endian integers and 64-bit pointers, the array is located at byte address 0x10000.

Question 3 (1 points): (see above) What is the contents of the byte at address 0x10005?

  1. 0x00

  2. 0x12

  3. 0x34

  4. 0x56

  5. 0x78

  6. 0xAB

  7. 0xCD

  8. 0xEF

Question 4 (1 points): (see above) The C expression array + 3 is a pointer containing what address?

  1. 0x10003

  2. 0x10006

  3. 0x1000C

  4. 0x10010

  5. 0x10012

Question 5 (1 points): If a calculation is undefined behavior in C, then ______.
Select all that apply

  1. compilers will translate the code to the most straightforward assembly, but what that assembly does may vary between platforms

  2. the same compiler may generate code which calculates different values depending on its optimization flags

  3. attempting to execute the calculation will result in a segmentation fault if it is run on Linux

  4. the result of the calculation may differ each time the resulting executable is run

For these questions, read section 4.2.2, 4.2.3 (but you may ignore details of HCL syntax) and 4.2.5.

Question 6 (1 points): (see above) Our textbook distinguishes combinatorial and sequential circuits. Which of the following are true about combinatorial circuits?
Select all that apply

  1. combinatorial circuits can only take two inputs

  2. a combinatorial circuit's output only depends on its input

  3. a combinatorial circuit's output can depend on its current input and a prior input

  4. combinatorial circuits are composed of logic gates and registers

Quiz 03

Question 1 (1 points): Consider the following HCLRS code:

x = [
    y > 10 : 100;
    y + z == 15 : 200;
    z > 10 : 300;
    1 : 400;
];

For which of the following values of y and z will the value of x be 200?
Select all that apply

  1. y = 4, z = 11

  2. y = 15, z = 0

  3. y = 0, z = 20

  4. y = 0, z = 15

Question 2 (1 points): In the register design we discussed in lecture, the value output by a register changes

  1. on the rising edge of the clock signal

  2. on the falling edge of the clock signal

  3. whenever the input value changes

  4. half a clock cycle after the input value changes

  5. a full clock cycle after the input value changes

Question 3 (1 points): Which of the following are more likely to be attributes of a processor implementing RISC-like instruction set than a CISC-like instruction set?
Select all that apply

  1. having separate instructions for moving values between memory and general purpose registers rather than allowing most instructions to access memory directly

  2. including an instruction that saves all general purpose registers to the stack

  3. having instructions that copy an variable-length string rather than requiring compilers to generate a loop of many instructions

Question 4 (1 points): In the register file design we discussed in lecture, writing to the register file is controlled by pairs of inputs. One input in each of these pairs specifies a 64-bit value and the other specifies an 8-bit register number. Suppose we have a processor which uses these inputs to change a value in the register file for some of the instructions it runs, but for other instructions it leaves the register file values unchanged. During clock cycles in which a register should not change, the processor should

  1. set the 8-bit register number input to the special value 0xF (15)

  2. make sure the 8-bit register number input is not connected to anything

  3. make sure the 64-bit value input is not connected to anything

  4. set the 64-bit value input to 0

  5. make sure the 64-bit vcalue input is set to the special value 0xFFFFFFFFFFFFFFFF (the maximum possible 64-bit unsigned integer)

For these questions, review sections 4.3.3-4.3.4 of the textbook. (If necessary for context, you may want to also review earlier parts of section 4.3.)

Question 5 (1 points): (see above) In the single-cycle processor design described by our textbook, the values stored in condition code registers are updated _______________ corresponding values are stored in the register file.

  1. earlier in the clock cycle

  2. at about the same time in the clock cycle

  3. later in the clock cycle

Question 6 (1 points): (see above) In the single-cycle processor design described by our textbook, during a pushq %rax instruction, the register file srcA and srcB inputs should be the register numbers corresponding to:

  1. %rax and %rsp

  2. %rax and %rbp

  3. %rsp (and the other input doesn't matter)

  4. %rax (and the other input doesn't matter)

  5. %rsp and %rsp (both inputs should be the same)

  6. %rax and %rax (both inputs should be the same)

Quiz 04

For these questions, consider the single-cycle processor design strategy described in our textbook and in lecture (the processor executes exactly one instruction per cycle), and the register file and memory components described lecture and our textbook.

Question 1 (1 points): (see above) When executing a call function instruction, the 64-bit address input of the data memory should be equal to

  1. does not matter because the instruction does not read from memory

  2. the result of a calculation performed by the ALU

  3. one of the 64-bit outputs of the register file

  4. the register number for %rsp

  5. the current output of the program counter register

  6. the 64-bit data output of the data memory

Question 2 (1 points): (see above) Executing a ret instruction requires several operations:

    1. reading the instruction from the instruction memory
    1. reading the current value of the stack pointer
    1. computing the current value stack pointer plus 8
    1. reading the return address from memory at stack pointer
    1. updating the stack pointer to its current value plus 8
    1. updating the program counter to the return address

In what order to these occur in the single-cycle hardware implementation?

  1. 1; then 2; then 3 and 4 in any order; then 5 and 6 at almost the same time

  2. 1; then 2; then 4; then 3; then 5 and 6 at almost the same time

  3. 1, 2, 3, and 4 in any order; then 5 and 6 at almost the same time

  4. 1; then 2; then 3; then 4; then 5; then 6

  5. 1; then 2; then 3; then 4; then 5 and 6 at almost the same time

  6. none of the above

Question 3 (1 points): (see above) In lecture, we described a processor design that could execute just the Y86 irmovq, rrmovq, mrmovq, and rmmovq instructions. Suppose we wanted to extend this processor to execute a new immovq instruction that would take a 64-bit constant and move it to a memory address specified with a 64-bit displacement and a base register. Which would be useful changes to make to the processor as part of adding this instruction?
Select all that apply

  1. making the instruction memory's output (i10bytes in HCLRS) wider than 80 bits

  2. adding a MUX to control the value input to the data memory (mem_input in HCLRS)

  3. adding an additional option to the MUX controlling the dstE (register number to write, reg_dstE in HCLRS) input to the register file

  4. adding an additional option to the MUX controlling the next R[dstE] (reg_inputE in HCLRS) input to the register file

  5. adding a MUX to control the input to the instruction memory (pc in HCLRS)

Question 4 (1 points): Consider a pipelined Y86 processor with two stages that performs the instruction memory and register file reads in the first stage and data memory reads and register file writes as part of the second stage. Suppose this processor is performing a memory read for an rmmovq instruction. While this is happening, the data memory's 64-bit value-to-write input (mem_input in HCLRS) will be equal to

  1. the output of a new register added to support pipelining

  2. one of the outputs of the register file

  3. the output of the program counter register

  4. part of the output of the instruction memory

  5. none of the above

Question 5 (1 points): Consider a pipelined processor with ten stages, where the clock cycle has 500 ps between rising edges. When an operation starts executing in the piepline, it will usually finish executing after

  1. 500 ps

  2. 1000 ps

  3. 4500 ps

  4. 5000 ps

  5. 5500 ps

  6. 6000 ps

  7. none of the above

Question 6 (1 points): Modifying a pipelined processor with 4 stages to instead have only 2 stages will generally increase ________.
Select all that apply

  1. the processor's cycle time

  2. the processor's instruction throughput

  3. the processor's instruction latency

  4. the number of registers in the processor

Quiz 05

Question 1 (1 points): Consider the following Y86 assembly snippet:

    addq %rax, %rbx
    subq %rbx, %rcx
    xorq %rdx, %rax
    rmmovq %rax, 8(%r8)
    andq %r8, %rbx

When executing on a five-stage pipelined proecssor like the one we described in lecture, there are data hazards because ________.

  1. the addq and rmmovq both try to read %rax

  2. the addq writes %rbx and the subq reads it

  3. the rmmovq and the addq both use %r8

  4. the addq writes %rax and the addq reads it

  5. the xorq writes %rax and the rmmovq reads it

  6. the addq writes %rbx and the andq reads it

Consider the following Y86 assembly snippet:

    subq %rcx, %rdx
    jle later
    addq %r8, %r9
    addq %r9, %r10

later:
    xorq %rdx, %rcx

Assume the initial values of %rcx and %rdx are set such that the jle is taken.

Question 2 (1 points): (see above) Consider a five-stage pipelined processor using the stages we discussed in lecture and uses stalling only to handle data hazards and control hazards. (Assume the whether a conditional jump is taken is not determined until near the end of the jump's execute stage.) If the subq instruction is fetched during cycle 0, then the xorq will complete its writeback stage during cycle _____.

  1. 5 or less

  2. 6

  3. 7

  4. 8

  5. 9

  6. 10 or more

Question 3 (1 points): (see above) Consider a five-stage pipelined processor using the stages we discussed in lecture and uses stalling and forwarding to handle data hazards, and branch prediction that predicts conditional jumps as always taken to handle control hazards. (Assume the processor users forwarding whenever it would not require substantially increasing the critical path length and therefore the cycle time.) If the subq instruciton is fetched during cycle 0, then the xorq will complete its writeback stage during cycle _____.

  1. 5 or less

  2. 6

  3. 7

  4. 8

  5. 9

  6. 10 or more

Consider the following Y86 assembly snippet:

    addq %rax, %rbx
    subq %rax, %rcx
    xorq %rbx, %rcx

Suppose the above assembly snippet is run a six-stage (in-order) pipelined processor which does not implement forwarding and uses the following stages:

The values of registers read are not available until the "Decode 2" stage.

Question 4 (1 points): (see above) To avoid data hazards when executing the above code using stalling only (and no forwarding), for how many cycles must a stall occur in the processor? (Count each cycle during which no new instruction can be started as a single stall.)

  1. 0

  2. 1

  3. 2

  4. 3

  5. 4

  6. 5 or more

Question 5 (1 points): (see above) To avoid data hazards when executing the above code using stalling and forwarding, for how many cycles must a stall occur in the processor? (Count each cycle during which no new instruction can be started as a single stall. Assume the processor uses forwarding whenever it would not require substantially increasing the critical path length and therefore the cycle time.)

  1. 0

  2. 1

  3. 2

  4. 3

  5. 4

  6. 5 or more

Quiz 06

Question 1 (1 points): Consider a 512B Cache with 4 blocks per set and 8 byte blocks. Which of the following hex values correspond to the index for address 0xABCD?

  1. 0xD

  2. 0xC

  3. 0x9

  4. 0x8

  5. 0xAB

  6. none of the above

Question 2 (1 points): Assume that you have a 32B direct mapped cache with 16B blocks with a LRU replacement policy. How many misses will result from reading the following addresses 0xABC 0xACE 0xACA 0xACF 0xAAA 0xACE ? Assume the cache starts off empty.

  1. 0

  2. 1

  3. 2

  4. 3

  5. 4

  6. none of the above

Question 3 (1 points): Increasing the associativity of the cache while keeping the number of set the same, will decrease the number of

  1. cold misses

  2. capacity misses

  3. does not change the number of misses

  4. none of the above

Question 4 (1 points): Consider the following series of read and write accesses. Where reads are marked with the letter R and writes are marked with the letter W. Assume at 64B fully associative cache with 4 blocks per set. This cache is using write-allocate policy and a LRU replacement policy. How many misses will the following access pattern generate: (W) 0xBAD (W) 0xABC (R) 0xBAC (R) 0xBOA (W) 0xBOA (W) 0xBED (W) 0xBEC? Assume the cache starts off empty.

  1. 0

  2. 1

  3. 2

  4. 3

  5. 4

  6. none of the above

For these quesitons, read section 5.2, the introduction to section 5.7 and the first paragraph of section 5.7.1, and section 5.7.3.

Question 5 (1 points): (see above) Suppose a superscalar, out-of-order processor can start 3 integer multiplications per cycle (using 3 pipelined integer multiplication circuits) and each integer multiplication takes 4 cycles to complete. By our textbook's terminology, what is the throughput bound on multiplications in this processor?

  1. about 0.3 cycles per element

  2. about 0.6 cycles per element

  3. 1 cycle per element

  4. about 1.3 cycles per element

  5. 2 cycles per element

  6. 3 cycles per element

  7. 4 cycles per element

Quiz 07

Consider the following C code:

    char array[4 * 1024];
    int sum;
    ...
    for (int k = 0; k < 2; ++k) {
        for (int i = 0; i < 4; i += 1) {
            sum += array[i * 1024] * array[16 + i * 16];
        }
    }

For each of the questions below, consider the behavior of cache during the outermost for loop. Assume the cache is empty when the for loop starts, only accesses to the array use the cache, and the neither the compiler nor the processor does that reorders or omits array accesses.

Assume the address of the array is a multiple of the cache size ( so array[0] is at the beginning of a cache block that maps to set index 0 in the cache).

Question 1 (1 points): (see above) With a 2KB direct-mapped cache with 16B cache blocks, how many cache misses will occur?

  1. 4

  2. 6

  3. 8

  4. 10

  5. 12

  6. 14

  7. 16

  8. none of the above

Question 2 (1 points): (see above) With a 128B 4-way set associative cache with 16B cache blocks and an LRU replacement policy, how many cache misses will occur?

  1. 4

  2. 6

  3. 8

  4. 10

  5. 12

  6. 14

  7. 16

  8. none of the above

Suppose a superscalar out-of-order processor is executing

    addq %r9, %10
    addq %r11, %rcx
    mrmovq 0(%rcx), %r8
    addq %r12, %rcx
    mrmovq 0(%rcx), %r9
    subq %r8, %r9
    mrmovq 8(%rcx), %r11

Question 3 (1 points): (see above) If the processor had enough functional units The mrmovq (%rcx), %r9 instructuion could be executed at the same time as
Select all that apply

  1. addq %r9, %r10

  2. addq %r11, %rcx

  3. mrmovq (%rcx), %r8

  4. addq %r12, %rcx

  5. subq %r8, %r9

  6. mrmovq 8(%rcx), %r11

Question 4 (1 points): (see above) If the processor uses register renaming where architectural registers are mapped to physical registers, then most likely ______.
Select all that apply

  1. %rcx in addq %r11, %rcx and in mrmovq 0(%rcx), %r8 will use different physical registers

  2. %r9 in addq %r9, %r10 and in mrmovq 0(%rcx), %r9 will use different physical registers

  3. %rcx in mrmovq 0(%rcx), %r8 and mrmovq 0(%rcx), %r9` will use different physical registers.

Quiz 08

Consider the following C function:

int size;  /* global variable, set elsewhere */

void example(int *A, int *B) {
    for (int j = 0; j < size; ++j) {
        for (int i = 0; i < size; ++i) { /* (1) */
            B[i] += A[i] * A[j];
        }
    }
}

Question 1 (1 points): (see above) Consider a version of the C function with the loops swapped:

void example_swapped_loops(int *A, int *B) {
    for (int i = 0; i < size; ++i) {
        for (int j = 0; j < size; ++j) {
            B[i] += A[i] * A[j];
        }
    }
}

Which of the following expressions are sufficient for the example_swapped_loops code to have an equivalent effect to the original code above? (Assume comparisons with pointers compare the pointer addresses.)
Select all that apply

  1. A != B && A != &size && B != &size

  2. A != B && &size < A && &size < B

  3. B == A + size && (&size < A || &size > A + size * 2)

  4. B == &size && A > B + size

Question 2 (1 points): (see above) Because of concerns about aliasing, a compiler often will not keep A[j] in register between iterations of the for loop labelled (1). What would be an effective way for a programmer to prevent this?
Select all that apply

  1. create a local variable Ajbefore the for loop labelled (1) and assign A[j] to it, and use this Aj variable instead of A[j] within the for loop

  2. create a local variable Aj_ptr before the for loop labelled (1) and assign &A[j] to it, and use *Aj_ptr instead of A[j] within the for loop

  3. unroll the for loop labelled (1)

  4. convert size from a global to local variable

Question 3 (1 points): If performed excessively, function inlining increases _____.
Select all that apply

  1. the size of an executable

  2. the number of instruction cache misses a program experiences

  3. the number of times values are written to and read from the stack

Quiz 09

Question 1 (1 points): When performing a context switch, from process A to process B, ____________ saves the value of registers like %rax in __________.

  1. the processor / the operating system's memory

  2. the processor / the exception table or interrupt vector table

  3. the operating system / the operating system's memory

  4. the operating system / the exception table or interrupt vector table

Question 2 (1 points): Which of the following are true about running an exception handler?
Select all that apply

  1. the exception handler runs in kernel mode

  2. when an exception is triggered by a particular instruction, the memory address of the exception handler run is part of that instruction

  3. when an exception is triggered by an external event, the processor saves the program counter somewhere before running the exception handler

  4. when an exception is triggered by an external event, the processor saves all general purpose registers (like %rax, %rcx, etc. on x86) to the current stack before running the exception handler

Suppose a system uses virtual memory where:

Question 3 (1 points): (see above) How large are physical page numbers in bits? Write your answer as a base-10 number.

Answer:

Question 4 (1 points): (see above) What is the virtual page number for the virtual address 0x12345? Write your answer as a hexadecimal number.

Answer:

Question 5 (1 points): (see above) Suppose the page table entry for the virtual address 0x10007 is valid and contains the physical page number 4. What is the physical address that corresponds to virtual address 0x10007? Write your answer as a hexadecimal number.

Answer:

Question 6 (1 points): (see above) If the page table base address is physical (byte) address 0x1000 then what is the physical (byte) address of the page table entry for virtual page number 3? Write your answer as a hexadecimal number.

Answer:

Quiz 10

Consider a system with:

Question 1 (1 points): (see above) If the page table base pointer contains the physical (byte) address 0x100000, then what is the physical (byte) address of the first-level page table entry for virtual address 0x10000? Write your answer as a hexadecimal number.

Answer:

Question 2 (1 points): (see above) If the page table base pointer contains the physical (byte) address 0x100000, then what is the physical (byte) address of the first-level page table entry for virtual address 0x80010000? Write your answer as a hexadecimal number.A

Answer:

Question 3 (1 points): (see above) If the base address for the second-level page table corresponding to virtual adress 0x10000 is (physical byte address) 0x40000, then what is the physical (byte) address of the second-level page table entry for virtual address 0x80010000? Write your answer as a hexadecimal number.

Answer:

Question 4 (1 points): (see above) On this system, accessing the virtual address 0x80341 accesses the same TLB set as accessing the virtual address _______.
Select all that apply

  1. 0x81341

  2. 0x90341

  3. 0xA0341

  4. 0x1234341

Question 5 (1 points): Which of the following is/are true about the process of swapping a page out of DRAM and into disk:
Select all that apply

  1. The valid bit of the page that is moved from DRAM to disk is set to 1

  2. The program whose page is getting swap from DRAM to disk was the program that triggered the fault.

  3. The Operating System chooses which page to move from DRAM to disk

  4. The operation of swapping page will be faster if the page being replace has not been modified.

Question 6 (1 points): Consider TLB cache in a 4-level paging machine. Which values are stored in the TLB?
Select all that apply

  1. Virtual Page Number

  2. The 1st Level Physical Page Number

  3. The Page offset

  4. Metadata for each the physical page

Quiz 11

Question 1 (1 points): Suppose a system uses 8192-byte pages. Assuming the L1 cache uses tags which store parts of physical addresses, with which of the following L1 cache configurations could it overlap TLB accesses and cache accesses?
Select all that apply

  1. a direct-mapped 32KB cache with 64B blocks

  2. a 16-way 1MB cache with a 64B blocks and a random replacement policy

  3. an 8-way 64KB cache with 64B blocks and an LRU replacement policy

  4. a direct-mapped 4KB cache with 64B blocks

Consider a system with a 16-entry, 2-way TLB with an LRU replacement policy and 4096-byte pages. A program runs on this system with an initially empty TLB and accesses one byte at the following virtual addresses in this order:

(Assume the pages corresponding to all virtual addresses are valid in the page table.)

Question 2 (1 points): (see above) Which of the following accesses are TLB misses?
Select all that apply

  1. the access to 0x05023

  2. the access to 0x0103F

  3. the access to 0xF8FF8

  4. the access to 0xF9FF8

  5. the second access to 0x01023

Question 3 (1 points): (see above) After these accesses complete, how many page table entries will the TLB store?

  1. 0

  2. 1

  3. 2

  4. 3

  5. 4

  6. 5

  7. 6

  8. 7

Question 4 (1 points): Increasing the size of pages will _____________.
Select all that apply

  1. increase the amount of storage required to implement a TLB that stores a particular number of entries

  2. increase the amount of data that can potentially be accessed by a program without any TLB misses

  3. increase the number of bits used for the page offset