If you have a floating-point number with a 2-bit exponent (bias 1) and a 3-bit fraction, which of the following numbers (shown in binary) is the largest finite number it can represent?
If you have a floating-point number with a 2-bit exponent (bias 1) and a 3-bit fraction, what is the smallest positive number (> 0) it can represent? Answers are shown in binary
Consider the following eight binary C operators: + - * / % ^ & |. Consider the 32 bits representing the result of "x operator y", where x and y are each either int or unsigned int. For how many of these 8 operators will those bits differ depending on the singed/unsigned nature of x and y? Your answer should be a single digit between 0 and 8:
Spring 2015 Quiz 3
Question 1 of 4
1.0 Points
How many total bytes of data can be stored in the (integer) IA32 program registers at one time? (a program register is one you can use as an operand when in programming in IA32 assembly)
The textbook uses ATT-format assembly, the default for most GNU tools. Some other tools use Intel-format assembly instead. Each of the following is true for only one of the two formats. Check those that are true of ATT-format assembly:
A.
there is a separate opcode for adding 32-bit values (addl) and 16-bit values (addw)
B.
register names are preceded by a percent-sign (e.g. %eax)
C.
memory addresses are written with square brackets and math operators (e.g. [edx+4])
D.
add A B (where A and B are registers) stores the sum of A and B into register A
E.
sub A B (where A and B are registers) evaluates B - A, not A - B
The "imul" instruction has only one operand, as in "imul \$101;", but the multiplication operation is implements requires two operands. The second operand is
A.
%eax
B.
%esp
C.
(%esp)
D.
12(%ebp)
E.
the same as the first (i.e., imul squares its operand)
In Java, C++, etc, there are types: a String is not the same as a Scanner, and so on. Types are distinct from "meaning": int x might *mean* your age and int y might *mean* your number of siblings, but the language doesn't stop you from saying "x = y" because they are both *type* int. In assembly
A.
There are no types at all
B.
Integers and floating-point numbers are distinct, but otherwise no types
C.
There are only a few built-in types, but assembly lets you create new ones
IA32 (also called x86) is CISC, not RISC, because (check all that apply)
A.
each instruction takes the same time to execute
B.
it has a lot of instructions or opcodes
C.
math operations can only operate with register operands (not memory)
D.
some instructions are encoded in just a single byte while others are much longer
E.
some instructions provide high-level abstractions, hiding lots of action under the hood
F.
there are many program registers
Spring 2015 Quiz 5
Question 1 of 4
1.0 Points
Two of the following are equivalent to the single-bit mux that the book denotes [ s : A; 1 : B; ], the other two are not equivalent to that mux. Mark the two that are:
A.
(s == A) || (s ^ B)
B.
(s == (A && B)) || (s != (A || B))
C.
s ? A : B
D.
(s && A) || (!s && B)
Question 2 of 4
1.0 Points
Consider the instruction "subl %edx, %ebx" passing through the five stages Fetch, Decode, Execute, Memory, Writeback. In which stage does the hardware retrieve the value stored in register %edx?
Consider the instruction "subl %edx, %ebx" passing through the five stages Fetch, Decode, Execute, Memory, Writeback. In which stage does the hardware decide where the result will be stored?
Not all stages are invovled in executing all instructions. Consider the instruction "subl %edx, %ebx" passing through the five stages Fetch, Decode, Execute, Memory, Writeback. Which (if any) stages are not involved in handling this instruction? Check any that apply
A.
Fetch
B.
Decode
C.
Execute
D.
Memory
E.
Writeback
Spring 2015 Quiz 6
Question 1 of 6
1.0 Points
Which of the following operations read a value from memory? Check all that apply
A.
nop
B.
rrmovl
C.
irmovl
D.
rmmovl
E.
mrmovl
F.
OPl
G.
jXX
H.
call
I.
ret
J.
pushl
K.
popl
Question 2 of 6
1.0 Points
Which of the following operations write a value to memory? Check all that apply
A.
nop
B.
rrmovl
C.
irmovl
D.
rmmovl
E.
mrmovl
F.
OPl
G.
jXX
H.
call
I.
ret
J.
pushl
K.
popl
Question 3 of 6
1.0 Points
Which of the following operations write a value to a program register? Check all that apply
A.
nop
B.
rrmovl
C.
irmovl
D.
rmmovl
E.
mrmovl
F.
OPl
G.
jXX
H.
call
I.
ret
J.
pushl
K.
popl
Question 4 of 6
1.0 Points
Which of the following operations read a value from a program register? Check all that apply
A.
nop
B.
rrmovl
C.
irmovl
D.
rmmovl
E.
mrmovl
F.
OPl
G.
jXX
H.
call
I.
ret
J.
pushl
K.
popl
Question 5 of 6
1.0 Points
The book discusses using the ALU just to forward values for some operations (e.g., their irmovl has the ALU compute 0 + valC) and to do math for other operations. The forwarding is just a design choice and could have been done otherwise, but the math is intrinsic to the operation of Y86. Which of the following operations use the ALU to do math?
A.
nop
B.
rrmovl
C.
irmovl
D.
rmmovl
E.
mrmovl
F.
OPl
G.
jXX
H.
call
I.
ret
J.
pushl
K.
popl
Question 6 of 6
1.0 Points
When building a chip, we can pick any clock speed we want; the goal is to make it as fast as we can while still being slow enough that no register grabs onto a value before that value has stabilized. Which of the following instructions would be most likely to determine the SEQ clock speed?
Suppose instruction A is followed by instruction B in the assembled code. There is a hazard between A and B if (check all that apply)
A.
A's inputs depend on B's outputs
B.
B's inputs depend on A's outputs
C.
Whether A runs depends on the outcome of B
D.
Whether B runs depends on the outcome of A
Question 4 of 5
1.0 Points
In the five-stage pipeline (F, D, E, M, W) we want E to have a second cycle to run its work. Assume there is a pipeline register before each stage (one before F, one before D, etc). How many of those 5 pipeline registers do we need to send the "stall" signal?
In the five-stage pipeline (F, D, E, M, W) we want E to have a second cycle to run its work. Assume there is a pipeline register before each stage (one before F, one before D, etc). How many of those 5 pipeline registers do we need to send the "bubble" signal?
Data can be stored in program registers, memory, or disk. Which of the following technologies (if any) is/are most commonly associated with memory? Check all that apply
A.
D Flip-flops
B.
DRAM
C.
Ethernet
D.
Magnetic disk
E.
Solid-state disk
F.
SRAM
Question 3 of 4
1.0 Points
Which of the following needs to be read and then re-written periodically in order to retain its storage? Check all that apply
A.
DRAM
B.
Magnetic disk
C.
Solid-state disk
D.
SRAM
Question 4 of 4
1.0 Points
Which of the following needs power in order to retain its storage? Check all that apply
A.
DRAM
B.
Magnetic disk
C.
Solid-state disk
D.
SRAM
Spring 2015 Quiz 9
Question 1 of 5
1.0 Points
Code has good spatial locality if
A.
each memory read is far from the address of the previous read
B.
each memory read is near the address of the previous read
C.
it uses a lot of memory overall
D.
it uses little memory overall
E.
there are gaps of unused memory padding the parts of memory it uses
F.
there are no gaps of unused memory between parts of memory it does use
Section 6.4 talks about blocks, caches, lines, and sets. Which one is contained by which other? Answer with four capital letters (B, C, L, and S) concatenated from outermost-to-innermost; for example, if believe that blocks contain caches which contain lines which contain sets, your answer should be BCLS
Question 5 of 5
1.0 Points
In a set-associative cache, which of the following can be determined from the memory address and cache organization alone (i.e., without knowing the cache contents)? Check all that apply.
A.
block offset
B.
set index
C.
tag
D.
which byte in the cache to access
E.
which line in the cache to access
F.
which set in the cache to access
G.
valid bit
Quiz 10 was not given
Spring 2015 Quiz 11
Question 1 of 3
1.0 Points
Which of the following is expected to run fastest? Assume N and M are large numbers.
A.
for(i=0; i<M; i+=1) for(j=0; j<N; j+=1) sum += a[i][j]
B.
for(j=0; j<N; j+=1) for(i=0; i<M; i+=1) sum += a[i][j]
C.
they're the same
D.
it depends on the cache organization (associativity, etc)
Which of the following are *not* tips for optimizing memory accesses given in the textbook? Check all that apply
A.
focus on the common case
B.
focus on inner loops
C.
get in the habit of performing cache optimizations everywhere
D.
reduce cache misses even if it means a few more memory accesses
E.
try to read memory in sequential order
F.
try to use data as often as possible once it has been read into memory
Spring 2015 Quiz 12
Question 1 of 3
1.0 Points
We want to loop over all i, j, and k (between 0 and 10240) and run the following: a[i][j] = b[i][k] * c[k][j] In order to maximize cache locality, in what order should the loops be placed?
Suppose function A is O(n) and for n=1 takes 100ms; function B is O(n^2) and for n=1 takes 1ms. Which of the following n do you expect to be the smallest for which A is faster than B?
Which of the following would you expect to be fastest? Assume we compile with the -O1 flag (i.e., the compiler stores variables in registers, but not fancier optimizations).
Which of the following would you expect to be fastest? Assume we compile with the -O1 flag (i.e., the compiler stores variables in registers, but not fancier optimizations).
Section 9.7.2 talks about how linux keeps track of memory regions with regard to read/write/execute permissions and shared memory. That information is also in the page table entries. Why should there be vm_area_structs if the same information is in the page table?
A.
having two copies provides fault tolerance if one fails
B.
one is for read/write/execute permissions, the other for user/kernel permissions
C.
one is for the MMU, the other for the OS
D.
the vm_area_struct is how you access a page table entry in C
Section 9.9 reviews how malloc and free work. One implementation of malloc and free has free do nothing and malloc simply keep a single pointer it increments each time it is called. This implementation has
Section 9.10 discusses garbage collector. These often perform reachability analysis, tracing all pointers recursively to find what parts of allocated memory are actually usable. The reachability analysis starts assuming that what is reachable?
A.
the most recent n allocation for some constant n
B.
the pointers in every stack frame ever allocated
C.
the pointers in every stack frame pushed but not yet popped
D.
the pointers in the current stack frame
E.
the pointers in the heap
F.
the pointers in the heap that have been allocated but not yet deallocated
G.
the pointers in the heap that have ever been allocated
A cache maps an address to a value. Virtual memory maps an address to another address. Which kind of cache is virtual memory (i.e., page tables, not the TLB) organized the most like?
A page table entry contains some permission information and some type of pointer. If our program is trying to dereference a 32-bit integer value stored in memory, page tables accessed along the way could point to (select all that apply)
A.
a page of data
B.
another page table
C.
some part of disk
D.
the 32-but integer in question
Spring 2015 Quiz 18
Question 1 of 4
1.0 Points
Which type of exception does *not* use the exception table?