Instructor: Kevin Skadron
Class meetings: Tu-Th 11:00-12:15 in OLS 011
Prerequisite: undergraduate computer architecture, covering at least pipelines and caches
This course will cover a set of prior hardware accelerators, such as database architectures; contemporary architectures, such as GPUs, TPUs, and FPGAs; and research proposals for potential new acceleration architectures, such as processing in memory, new machine-learning accelerators, and so on.
Assignments will consist of readings, group presentations of readings for class discussion, participation via comments written before class, scribe duties for the in-class discussion, and a research project. Group projects are encouraged. The topic and plan for the project should offer the potential for publication.
The course grade will be based approximately on:
Honor code terms: All work must correctly attribute sources. All group work must represent equal effort from all partners--deviations from equal effort must be documented and should be discussed with me first. Projects must represent original work.
Last updated: 3 Nov. 2022