In article <CA81Hu.IsD@ryn.mro4.dec.com> bhandarkar@msbcs.enet.dec.com (Dileep Bhandarkar) writes:
>
>In article <1993Jul13.174722.10241@eecs.nwu.edu>, shil@nasser.eecs.nwu.edu
(Lei Shi) writes...
>> I am looking for the following information about the DEC 3000 AXP model 400.
>> My questions are:
>>1. What are the read miss penalty and write miss penalty in terms of the CPU
>>cycles for the first level cache if the data is in the second level cache?
>>2. What are the read miss penalty and write miss penalty in terms of the CPU
>>cycles for the second level cache if the data is in the main memory?
>>
>The second level cache access time is 5 cycles. Memory access time is 27 cycles.
>Clock rate is 133 MHz.
My measurement for TITAN2-400 (Alpha 133MHz) tells,
1. read miss penalty is 8 cycles for read, 12 cycles for write for the
first level cache when the data is in the second level cache.
2. read miss penalty is 12 cycles for read, 40 cycles for write when
the data is only in the memory.
Toshinori Maeno
Tokyo Institute of Technology
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