Re: Looking for info. on DEC 3000 AXP 400

From: Toshinori Maeno (maeno@is.titech.ac.jp)
Date: Fri Jul 16 1993 - 05:47:01 CDT

Sorry for my mistake in my last posting.

In article <1993Jul16.104143.27476@is.titech.ac.jp> maeno@is.titech.ac.jp (Toshinori Maeno) writes:

>My measurement for TITAN2-400 (Alpha 133MHz) tells,
> 1. read miss penalty is 8 cycles for read, 12 cycles for write for the
                                              ==
                                              34 is correct

>first level cache when the data is in the second level cache.
>
> 2. read miss penalty is 12 cycles for read, 40 cycles for write when
>the data is only in the memory.

Toshinori Maeno
Tokyo Institute of Technology

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