These are possible topics for the exam. Given that it is a 75-minute exam, it is likely that not all of these topics will actually make it on the exam.
Memory hierarchy
cache lookup: tag/index/offset
TLBs and page tables
interaction between TLB lookups and cache lookups
cache parameters and performance tradeoffs
victim caches
stream buffers and/or prefetching
interpreting HW1-style benchmark results
Pipelining
throughput versus latency tradeoff
hazards, data and control
forwarding and stalls
instruction scheduling and loop unrolling
Multiple/out-of-order issue
the VLIW concept (what is it? when is good? when is it bad?)
precise exceptions/reorder buffer
register renaming
reservation stations/instruction queues
static branch prediction
dynamic branch prediction
reasoning about out-of-order processor throughput/efficiency
hardware multithreading
Multicore
processor network designs
MOESI-like cache coherency protocols
directories for cache-coherence
relaxed memory models (what are they? when are they good? when are they bad?)