Submissions are welcomed on any topic pertaining to temperature-aware architecture, including but not limited to:

• Modeling and validation
• Thermal implications of novel architectures, design styles, or technologies
• Dynamic thermal management for the CPU, CMPs, SoCs, other system components, clusters, data centers, etc.
• Circuit/architecture/OS cooperation
• Scheduling techniques
• Sensitivity of other metrics to operating temperature
• Application-specific thermal optimizations
• New benchmark applications and sampling techniques for thermal studies
• Workload characterization
• Interaction of thermal management, energy efficiency (especially leakage), and voltage stability
• Interaction of thermal management and other runtime optimizations
• All architecture-related aspects of temperature-dependent reliability effects
• Interaction of thermal management with real-time requirements
• Interaction of manufacturing, packaging, and cooling with architecture
• Architecture impacts of novel cooling techniques (from chip-level to data-center level)
• New thermal-sensor architectures
• Position papers suggesting how thermal engineers and architects can collaborate, preferably with concrete examples.

The paper should be in IEEE conference format and at most ten pages in length including all figures, references, etc. Excessively long papers will be rejected without review.

Submission deadline: April 4, 2005, extended to April 18, 2005, 7:00 *am* EDT
Author notification: May 3, 2005
Final manuscripts: May 20, 2005

Detailed formatting instructions and LaTeX/Word templates are available here.
Online submission can be found here.

Please send questions and paper submisisons to: skadron |at| cs DOT virginia DOT edu