This page contains quizzes given Fall 2015. For other semesters see the main old quizzes page

Fall 2015 Quiz 01

Part 1 of 1 -

Fall 2015 Quiz 02

Part 1 of 1 -

Fall 2015 Quiz 03

Question 1 of 3

1.0 Points

Our textbook and most GNU tools using ATT format assembly, but 2150 uses Intel format assembly instead. Each of the following is either true for ATT or Intel format, but not both; which are true of ATT format assembly? Select all that apply.

A. the destination comes first (like C's binary = operator)
B. there is a different add command for 16-bit operands than for 64-bit operands
C. parentheses dereference a point (like C's unary * operator)
D. registers are identified with a percent-sign

Question 2 of 3

1.0 Points

The textbook shows two ways to translate a while loop to use goto statements: jump to middle and guarded do. Optimizing compilers prefers guarded do. This is because

A. guarded do executes fewer labels
B. guarded do executes fewer jumps
C. guarded do executes fewer conditional checks
D. none of the above

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Question 3 of 3

1.0 Points

The call instruction changes which of the following registers? Select all that apply.

A. all callee-save registers
B. all caller-save registers
C. the base pointer
D. the program counter
E. the stack pointer

Fall 2015 Quiz 04

Question 1 of 3

1.0 Points

Most jumps can only go to compile-time-known addresses, but the C switch command jumps to a runtime-computed address using jmp *label(offset) syntax x86-64 assembly. Which Y86-64 command moves the program counter to a runtime-computed address?

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Question 2 of 3

1.0 Points

Which of the following Y86-64 assembly snippets does the same thing as cmovle %rbx, %rax?

A. rrmovq %rbx, %rax
B. cmovg %rax, %rbx
C. jle after rrmovq %rbx, %rax after:
D. jmp after before: rrmovq %rbx, %rax after: jle before
E. One or more of the above
F. None of the above

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Question 3 of 3

1.0 Points

The pushq operation (in either x86-64 or Y86-64) does which of the following?

A. increases the value stored in rsp by 8
B. increases the value stored in rsp by 4
C. increases the value stored in rsp by 1
D. does not change the value stored in rsp
E. decreases the value stored in rsp by 1
F. decreases the value stored in rsp by 4
G. decreases the value stored in rsp by 8

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Fall 2015 Quiz 05

Question 1 of 5

1.0 Points

The C operators & and && function differently in that both (1) & is bit-wise but && is logical instead; and (2) && short-circuits, only evaluating the second operand if the first operand was true. The AND gates and HCL && operator described in the book

A. are bit-wise like C's &
B. are logical like C's &&
C. require single-bit operands, so you can't tell the difference

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Question 2 of 5

1.0 Points

A. do not short-circuit (like C's &, which does not short-circuit)
B. do short-circuit (like C's &&, which does short-circuit)
C. require single-bit operands, so you can't tell the difference

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Question 3 of 5

1.0 Points

Supposed I have a register and want to be able to "stall" it, preventing it from storing new values when there is a 0 on wire X. While the register is stalled, I want it to keep whatever value it had when I stalled it until X has a 1 again, at which point it may resume normal operation. To do this, I should

A. use (X AND clock signal) as the registers' clock input.
B. use (X OR clock signal) as the registers' clock input.
C. use (X XOR clock signal) as the registers' clock input.
D. use (X AND input) as the registers' data input.
E. use (X OR input) as the registers' data input.
F. use (X XOR input) as the registers' data input.
G. None of the above will work.

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Question 4 of 5

1.0 Points

Supposed I have a register and want to be able to "bubble" it, such that if there is a 0 on wire X then it outputs a 0 no matter what its data input is. To do this, I should

A. use (X AND clock signal) as the registers' clock input.
B. use (X OR clock signal) as the registers' clock input.
C. use (X XOR clock signal) as the registers' clock input.
D. use (X AND input) as the registers' data input.
E. use (X OR input) as the registers' data input.
F. use (X XOR input) as the registers' data input.
G. None of the above will work.

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Question 5 of 5

1.0 Points

In the HCL described in the book, the square bracket notation

A. defines a list of values
B. retrieves a value from a list
C. concatenates several wires into a wider wire
D. splits a wide wire into one or more narrower wires
E. turns "a : b;" into C-notation "a ? b :" and appends a trailing "0"
F. turns "a : b;" into C-notation "((~a) & b) \|" and strips the trailing "\|"

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Fall 2015 Quiz 06

Part 1 of 1 -

Figure 4.18 of the textbook gives a sequential implementation of the Y86 instruction OPq. Suppose we wanted to have a *new* operator in Y86, iOPq, in which one of the two operands was an immediate value and the other was a register. The questions below give pieces of OPq and ask about changes associated with implementing iOPq.

Fall 2015 Quiz 07

Part 1 of 1 -

Consider adding a new instruction "jpr" to SEQ that jumps to a program register. A use of the instruction might look like "jpr %rdi"

Fall 2015 Quiz 08

Question 1 of 5

1.0 Points

Consider S, a computer without pipelining, and P, the same computer with pipelining. Assuming that pipelining is the only change made, which will complete a single-instruction program run faster?

A. S
B. P

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Question 2 of 5

1.0 Points

Consider S, a computer without pipelining, and P, the same computer with pipelining. Assuming that pipelining is the only change made, which will complete a 50-instruction program run faster?

A. S
B. P

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Question 3 of 5

1.0 Points

Given a pipelined computer, if I replace the pipeline registers with ones that run faster, making appropriate changes to the clock but leaving the rest of the hardware untouched, I will

A. increase throughput
B. not change throughput
C. decrease throughput

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Question 4 of 5

1.0 Points

Given a pipelined computer, if I replace the pipeline registers with ones that run faster, making appropriate changes to the clock but leaving the rest of the hardware untouched, I will

A. increase latency
B. not change latency
C. decrease latency

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Question 5 of 5

1.0 Points

If registers had no delay at all,

A. nonuniform partitioning would not impact latency
B. nonuniform partitioning would not impact throughput
C. deep pipelines would not have diminishing returns re. latency
D. deep pipelines would not have diminishing returns re. throughput

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Fall 2015 Quiz 09

Part 1 of 2 -

Question 1 of 8

1.0 Points

Which of the following are features of hardware? Select all that apply.

A. data dependencies
B. control dependencies
C. data hazards
D. control hazards

Question 2 of 8

1.0 Points

Which of the following are features of software? Select all that apply.

A. data dependencies
B. control dependencies
C. data hazards
D. control hazards

Part 2 of 2 - Stages vs Regsiters

Each logical stage in a pipeline lies between two pipeline registers. Suppose we have stages S1, S2, and S3 and registers R1 and R2 laid out like S1→R1→S2→R2→S3. Note: part of this question depends on the fact that "bubble" and "stall" mean different things when applied to register (like R1) vs stages (like S1).

Fall 2015 Quiz 10

Question 1 of 6

0.5 Points

Static RAM is typically faster than dynamic RAM

A. True

B. False

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Question 2 of 6

0.5 Points

Static RAM is typically cheaper than dynamic RAM

A. True

B. False

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Question 3 of 6

0.5 Points

Which kind of RAM needs to be read and re-written to retain its value?

A. Static
B. Dynamic
C. Both
D. Neither

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Question 4 of 6

0.5 Points

Which kind of RAM retains its value if power is lost?

A. Static
B. Dynamic
C. Both
D. Neither

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Question 5 of 6

1.0 Points

(data memory) Temporal locality is when

A. lots of code runs at the same time
B. consecutive instructions are executed from the same method
C. each memory access has an address close to previously-accessed addresses
D. the same address is accessed repeatedly in close succession

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Question 6 of 6

1.0 Points

(data memory) Spatial locality is when

A. the same address is accessed repeatedly in close succession
B. each memory access has an address close to previously-accessed addresses
C. consecutive instructions are executed from the same method
D. lots of code runs at the same time

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Fall 2015 Quiz 11

Question 1 of 6

1.0 Points

Which of the following implements a single array of lines?

A. direct-mapped cache
B. fully-associative cache
C. set-associative cache

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Question 2 of 6

1.0 Points

Which of the following implements a single set of lines?

A. direct-mapped cache
B. fully-associative cache
C. set-associative cache

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Question 3 of 6

1.0 Points

Given 64-bit addresses, 8-byte blocks, 4-element sets, and 16 sets, how long is the tag? Answer as a positive base-10 integer like 3 or 127.

Question 4 of 6

1.0 Points

The dirty bit is used for (pick the best answer)

A. direct-mapped caches
B. fully-associative caches
C. set-associative caches
D. write-through caches
E. write-back caches

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Question 5 of 6

1.0 Points

A conflict miss is when

A. a recent memory access mapped to the same line but a different tag of a direct-mapped cache
B. a recent memory access mapped to the same line but a different tag of a fully-associative cache
C. a recent memory access mapped to the same tag but a different line of a direct-mapped cache
D. a recent memory access mapped to the same tag but a different line of a fully-associative cache

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Question 6 of 6

1.0 Points

Which of the following is likely to increase the cache-friendliness of code the most?

A. increase set sizes
B. increase block sizes
C. maximize spatial locality
D. maximize temporal locality

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Fall 2015 Quiz 12

Question 1 of 5

1.0 Points

(section 5.1) Why do twiddle1 and twiddle2 not get the same optimization?

A. it may be the case that xp == yp
B. it may be the case that xp == yp
C. using one complicated line makes the code harder for the compiler to understand
D. using two simpler lines makes the code harder for the compiler to understand

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Question 2 of 5

1.0 Points

(section 5.2) The textbook's CPE (cycles per execution) is about

A. additive constants
B. big-O
C. multiplicative constants
D. none of the above

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Question 3 of 5

1.0 Points

(section 5.4) The core idea of "eliminating loop inefficiencies" is to

A. don't repeat computations that always give the same result
B. focus optimization on the inner-most loop
C. increase locality of your code
D. none of the above

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Question 4 of 5

1.0 Points

(section 5.5) Why does reducing procedure calls save us time?

A. It reduces control dependencies in the code
B. It reduces data dependencies in the code
C. It enables more compiler optimizations
D. We do less computational work overall

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Question 5 of 5

1.0 Points

(section 5.8) Loop unrolling primarily benefits us by

A. increasing temporal locality
B. increasing spatial locality
C. reducing procedure calls
D. reducing time spent in the ALU
E. reducing time spent in Memory

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Fall 2015 Quiz 13

Question 1 of 4

1.0 Points

Which of the following terms is a general term that includes the others as sub-kinds?

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Question 2 of 4

1.0 Points

Which of the following refers to something created by an event external to the CPU?

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Question 3 of 4

1.0 Points

Which of the following is always created intentionally by user code?

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Question 4 of 4

1.0 Points

Which of the following is handled by the exception table?

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Fall 2015 Quiz 14

Question 1 of 6

1.0 Points

Let C be the set of all possible concurrent processes and P be the set of all possible parallel processes.

A. C is a subset of P
B. P is a subset of C
C. the intersection of C and P is empty
D. the intersection of C and P is non-empty but smaller than either C or P

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Question 2 of 6

1.0 Points

If you run two programs at the same time and the two use the same addresses,

A. both programs will access the same memory (one can change the other's memory)
B. each program will have its own copy of memory (neither can change the other's memory)
C. the kernel will kill the programs because they conflict
D. the linker will change the addresses so they no longer overlap

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Question 3 of 6

0.5 Points

Most processors contain a special one-bit register called the "mode bit" that distinguishes between kernel mode and user mode. True or false: when in user mode, programs can run some but not all of the assembly instructions they can run in kernel mode.

A. True

B. False

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Question 4 of 6

0.5 Points

True or false: when in user mode, programs can access some but not all of the addresses that they can access in kernel mode.

A. True

B. False

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Question 5 of 6

0.5 Points

True or false: when in user mode, programs can access some but not all of the file system locations that they can access in kernel mode.

A. True

B. False

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Question 6 of 6

1.0 Points

Which of the following will not cause a context switch?

A. accessing memory that is not in the cache
B. running the assembly instruction "int"
C. the disk telling the CPU that data is available to read
D. too much time elapsing since the last context switch
E. writing to read-only memory

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Fall 2015 Quiz 15

Question 1 of 5

1.0 Points

Select all that apply:

A. virtual address space can be smaller than physical address space
B. virtual address space can be the same size as physical address space
C. virtual address space can be larger than physical address space

Question 2 of 5

1.0 Points

In caches the fundamental unit of storage is a line or block. In virtual memory it is a ____ (give a one-word lower-case answer without punctuation)

Question 3 of 5

0.0 Points

(select all that apply) A PTE describes where a particular range of addresses in virtual memory is stored. It can be

A. in physical memory
B. on the disk
C. neither in physical memory or on disk

Question 4 of 5

1.0 Points

A page fault is a type of exception, as described in chapter 8

True

False

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Question 5 of 5

1.0 Points

A PTE describes where a particular range of addresses in virtual memory is stored, as well as all but one of the following; which one is not part of PTE?

A. if code may read from the memory in question
B. if code may write to the memory in question
C. if the memory in question may be accesses by non-kernel code
D. all of the above are part of a PTE

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Fall 2015 Quiz 16

Question 1 of 5

1.0 Points

The page table maps between virtual and physical addresses; it is stored

A. as a file on disk
B. in memory
C. on the CPU
D. none of the above

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Question 2 of 5

1.0 Points

The PTBR contains an address. This address is in a

A. virtual address space
B. physical address space
C. none of the above

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Question 3 of 5

1.0 Points

A page table is used like an array; its index is

A. a whole physical address
B. part of a physical address
C. a whole virtual address
D. part of a virtual address

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Question 4 of 5

1.0 Points

A TLB is

A. a cache for storing page tables
B. a cache for storing page table entries
C. part of each page table
D. part of each page table entry

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Question 5 of 5

1.0 Points

For multi-level page tables, each process has several page tables for its memory. What is the size of each of these page tables?

A. Each page table is smaller than a page
B. Each page table is is the same size as a page
C. Each page table is larger than a page
D. Within a process, some page tables can be smaller and some larger
E. Within a process each page table is the same size, but between processes some can be larger and some smaller

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Fall 2015 Quiz 17

Part 1 of 1 -

Compare and contrast memory caching (where slow RAM and fast L# caches interact to provide the illusion of a large, fast memory) and virtual memory (where slow disk and fast RAM interact to provide the illusion of large, fast memory). Several questions refer to "the faster store" (meaning the L# cache for caches, the RAM for virtual memory) and the "slower store" (meaning RAM for caches, disk for virtual memory). Assume for these questions that caching is implemented on a computer without virtual memory and virtual memory is implemented on a computer without caching.

The table below summarizes the paragraph above:

	Memory Caching	Virtual Memory
"the faster store"	L# cache	RAM
"the slower store"	RAM	Disk
assumptions:	The computer has no virtual memory	The computer has no memory caching

Fall 2015 Quiz 01

Part 1 of 1 -

Question 1 of 3

Question 2 of 3

Question 3 of 3

Fall 2015 Quiz 02

Part 1 of 1 -

Question 1 of 4

Question 2 of 4

Question 3 of 4

Question 4 of 4

Fall 2015 Quiz 03

Question 1 of 3

Question 2 of 3

Question 3 of 3

Fall 2015 Quiz 04

Question 1 of 3

Question 2 of 3

Question 3 of 3

Fall 2015 Quiz 05

Question 1 of 5

Question 2 of 5

Question 3 of 5

Question 4 of 5

Question 5 of 5

Fall 2015 Quiz 06

Part 1 of 1 -

Question 1 of 5

Question 2 of 5

Question 3 of 5

Question 4 of 5

Question 5 of 5

Fall 2015 Quiz 07

Part 1 of 1 -

Question 1 of 5

Question 2 of 5

Question 3 of 5

Question 4 of 5

Question 5 of 5

Fall 2015 Quiz 08

Question 1 of 5

Question 2 of 5

Question 3 of 5

Question 4 of 5

Question 5 of 5

Fall 2015 Quiz 09

Part 1 of 2 -

Question 1 of 8

Question 2 of 8

Part 2 of 2 - Stages vs Regsiters

Question 3 of 8

Question 4 of 8

Question 5 of 8

Question 6 of 8

Question 7 of 8

Question 8 of 8

Fall 2015 Quiz 10

Question 1 of 6

Question 2 of 6

Question 3 of 6

Question 4 of 6

Question 5 of 6

Question 6 of 6

Fall 2015 Quiz 11

Question 1 of 6

Question 2 of 6

Question 3 of 6

Question 4 of 6

Question 5 of 6

Question 6 of 6

Fall 2015 Quiz 12

Question 1 of 5

Question 2 of 5

Question 3 of 5

Question 4 of 5

Question 5 of 5

Fall 2015 Quiz 13

Question 1 of 4

Question 2 of 4

Question 3 of 4