• Semester preview: Layers of abstraction
• Why C?
• Powers of Two
• Endianness
• Program Memory Layout (Stack, Heap, etc.)
• Compilation Steps and Object Files

• Compilation Steps and Object Files (finish)
• AT&T syntax assembly
• X86-64 calling convention
• LEA (load effective address)
• If, loop-to assembly
• X86 condition codes (start)
  • cmpq versus subq
  • testq %rax, %rax

• X86 condition codes (finish)
  • SF, ZF
• Loop-to-assembly (revisited)
• C types
• Truth in C, &&, ||
• Pointer Arithmetic

• Arrays versus Pointers
• Command Line Tips
• printf
• struct and typedef struct
• malloc, free, dynamic arrays
• Problematic things:
  • Unsigned/signed comparision
  • Undefined behavior

• CISC versus RISC
• Y86-64 instruction set
• Y86-64 machine code

• Bitwise and/or/xor
• Bit shifting (left, logical right)
• Bit puzzle strategies
  • Mask and shift
  • Parallelism example: any-bit-set with &
• Arithmetic shift

• SEQ components
  • Registers generally and the PC
  • Instruction and data memory
  • Register file
  • MUXes
• Simple processors: nop, addq, jmp, mov

• HCLRS intro
  • HCLRS built-in components
  • Defining register banks
  • Wires and wire widths
  • MUXes
• Simple processors in HCLRS
• mov CPU

• SEQ “stages”
• Less simple processors: ??mov
• Handling push, pop, ret, call, etc.

from 11am class:

• notes text file
• drawing

from 2pm class:

• notes text file
• drawing

• pipelining idea (laundry example)
• latency and throughput
• register tolerances and diminishing pipelining returns
• the textbook’s five-stage pipelined processor
• pipelining the addq CPU
• critical paths and circuit speeds

• HCL register naming
• addq CPU pipelined in HCL
• SEQ to PIPE
  • Where to add registers/what registers to add?
  • Rules for programming pipeline stages
• Hazards — Data and Control
• Stalling as a Hazard Solution

• Forwarding
  • Motivation, HCL example
• Forwarding paths exercies
• Branch prediction and squashing

• Remaining problem: The Load-Use Hazard
• Implementing stalling/squashing in HCLRS
  • bubble and stall signals
• Preview: Out-of-Order, Multiple Issue Execution
• Better branch prediction ideas
• The Memory Hierarchy Idea
• Locality
  • Spatial versus Temporal
  • Examples with Loops

• Direct-Mapped Caches
• Tag/Index/Offset for Direct-Mapped Caches
• Set-associative caches
• Tag/Index/Offset for set-associative caches

• Replacement policies
• Write policies and write buffers
• Cache parameters and performance
  • Average memory access time (AMAT)
• C code and cache misses

• Loop reordering
• Cache blocking

• Compiler limitations
  • Aliasing
  • Seperate compilation
  • Code Size versus Time
• Inlining
• Removing redundant operations
• Loop Unrolling

from 11am class:

• notes text file
• drawings: 1 2 3 from 2pm class:
• notes text file
• drawings: 1 2 3

• Loop Unrolling Versus Cache Blocking
• Rotate assignment intro
  • RIDX and C macros
  • partners
• Multiple Issue, Out-of-Order CPUs
  • What instruction queues do
  • The latency bound
  • Functional/execution units
  • Multiple accumulators, reassociation
• Addressing efficiency

• Vector intructions
  • What they are, examples
  • The Intel intrinsics
• Profilers
• Processes
  • Time multiplexing and measuring an empty loop
  • Contexts and context switches

• Processes continued
  • Address spaces — illusions of dedicated memory
  • Threads — illusions of dedicated CPU
  • Process = Thread(s) + Address Space
• System calls
  • Linux system call calling convention and example
  • System calls must trust no one
• Lack of consistent exception/kernel mode terms
• Virtual versus physical addresses
  • What a “4GB address space” means
• Four-page example page table example
  • Splitting addresses: page number, page offset

• Four-page example page table example continued
  • Simple page tables
• Kernel-mode-only pages (e.g. for page table switching code)
• Address splitting and page counting examples
• Storing/using page tables in memory
  • Memory management units location in the CPU pipeline
• Preview: single-level tables too big, memory accesses too slow
  • Remark: how 48-bit virtual addresses on 64-bit system?
• Page table lookup exercises
• Page permission bits
  • Motivation: shared read-only code
• Page table ‘tricks’ (not failing on a page fault):
  • Allocating space on demand
  • Swapping
    • Motivation: HDD/SSD performance
    • Example timeline
  • Implementing write-back policies
  • Implementing swapping replacement policies
  • Copy-on-write

• Multi-level page tables
  • Motivation: impossibly huge single-level page tables
  • Motivation: large holes
  • Two-level page table lookup
  • Note that parts of VPNs aren’t VPNs
  • Splitting addresses for multi-level tables
  • Page table lookup exercises
  • x86-64 page table structure
  • Page table space exercises

• TLBs
  • Motivation: temporal locality in PTE accesses
  • TLBs versus L1 caches
  • TLBs and the memory management unit
  • TLB layout, lookup process
  • TLB + multi-level page table address splitting exercises
  • Changing page tables and TLB invalidation

• 11am: notes, drawing 1 2
• 2pm: notes, drawing 1

7PM.

Wilson 402.

conflict form