This page contains quizzes given Spring 2016. For other semesters see the main old quizzes page

Spring 2016 Quiz 0

Question 1 of 4

1.0 Points

How are C and C++ related?

A. C is a subset of C++
B. C is a superset of C++
C. neither
D. both

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Question 2 of 4

1.0 Points

Some of the tools we use in this class use strict ANSI-compliant C. You can get this version by running "gcc -ansi -pedantic-errors" or "clang -ansi -pedantic-errors". In this standard one (and only one) of the following is an error. Which one?

A. int f() { return 33.30f; }
B. void f() { int x = 3, y = x+1; }
C. float f() { return 3330; }
D. void f() { return; }
E. void f() { int x = 3; int y = x+1; }
F. void f() { int x, y; x = 3; y = x+1; }
G. void f(void) {}
H. void f() { int x; x = 3; int y = x+1; }

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Question 3 of 4

0.0 Points

Suppose you have a variable declared as an array (e.g., "int y[32]") and another declared as a pointer (e.g., "int *z"). In what way do the two variable differ?

A. they behave the same in C, but are different under the hood
B. you can add an offset to the pointer (like "z + 2") but not to the array
C. you can use square brackets to index the array (like "y[2] = 3"), but not the pointer
D. y has a length field, but z does not
E. you can use * to dereference the array (like "*z") but not the pointer
F. they are identical

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Question 4 of 4

1.0 Points

Spring 2016 Quiz 1

Question 1 of 4

1.0 Points

Suppose a process spends 1 second doing task A, then 3 doing B, then 6 doing C. Which of the following will give the biggest speedup?

A. Do A, B, and C in parallel
B. Speed up the B and C parts by a factor of 2
C. Speed up C by a factor of 3
D. Split C in half, and parallelize three-ways: (A then B), (C1), and (C2) in parallel but add a 2 second set-up time before any of them can start and a 0.5-second cleanup time after C1 and C2 have finished (potentially in parallel with the A-then-B process).

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Question 2 of 4

1.0 Points

Given some type T (where sizeof(T) ≠ 1) and a variable declared "T *x", which of the following is equivalent to "x[3]"?

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Question 3 of 4

1.0 Points

Suppose I have a type declared "typedef struct range_t { int length; int *ptr; } range;" and a function declared "range foo()" that returns a range with length=8 and an 8-element heap-allocated array pointed to by ptr. How much heap memory does foo need to use? Select all that apply (i.e., the answer should be the sum of the options you pick).

A. 32 bytes for the array
B. 4 bytes for the length
C. 8 bytes for the pointer (assuming this is a 64-bit machine)
D. space for foo's activation record
E. more memory not listed above

Question 4 of 4

1.0 Points

How much memory is used to represent the string "3330" in C? Answer as an integer number of bytes (expressed in the usual base-10 format with no leading zeros). Ignore alignment and other nuances of memory that we have not discussed.

Spring 2016 Quiz 2

Part 1 of 1 -

Reminder: in most C dialects, >> is a logical shift for unsigned types and an arithmatic shift for signed types

Spring 2016 Quiz 3

Part 1 of 1 -

Spring 2016 Quiz 4

Part 1 of 1 -

Spring 2016 Quiz 5

Question 1 of 4

1.0 Points

While can be converted to assembly either as jump-to-middle or as guarded-do, the latter of which the book describes as enabling other optimizations. Without those extra optimizations, which one involves executing more instructions?

A. jump-to-middle involves more executed instructions
B. guarded-do involves more executed instructions
C. they involve the same number of executed instructions

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Question 2 of 4

1.0 Points

The text discusses stack usage with call and ret, but this is mostly convention, not forced behavior. Which of the following jumps to an address that is stored in a register?

A. call L; L: pop %rax
B. ret; pop %rax
C. push %rax; ret
D. push %rax; call L; L: nop

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Question 3 of 4

1.0 Points

Y86-64 has the following features. Select all that suggest Y86-64 is a RISC architecture:

A. 26 instructions (counting all the flavors of jXX, etc)
B. Each instruction does one thing (one move, one simple math operation, etc)
C. Instruction sizes may be 1, 2, 9, or 10 bytes
D. Exactly three address formats: 42, 42(%rax), and (%rax).
E. OPq only accepts register operands
F. Any assembly operation may follow any other
G. Condition Codes

Question 4 of 4

1.0 Points

In a little-endian machine, select all that apply:

A. The low-order byte of an integer is placed at a smaller address than the high-order byte of that same integer
B. For an array x, x[1] is placed at a smaller address than x[0]
C. For a struct { int x; int y; }, y is placed at a smaller address than x

Spring 2016 Quiz 6

Part 1 of 1 -

Suppose we were creating an instruction ipushq that moves from an immediate to the stack. Figures 4.18 and 4.20 in the textbook describe irmovq (which moves from an immediate) and pushq (which moves to the stack). Using them as a reference, answer the following questions about how we would describe the behaviour of ipushq.

Suggestion: write out a full description of ipushq on paper and then answer the questions below.

Spring 2016 Quiz 7

Question 1 of 4

1.0 Points

Section 4.3.3 "SEQ Timing" emphasizes that (1) no stage depends on the results of a later stage and (2) no instruction reads a register or memory value after writing it. Which of the following would violate one of these two rules?

A. allowing immediate operands to arithmetic operations
B. allowing immediate-to-memory moves
C. allowing memory operands to arithmetic operations
D. allowing memory-to-memory moves

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Question 2 of 4

1.0 Points

irmovq moves from an immediate value (which can be found in valC) to the register file, but neither figure 4.23 nor the up-close view of memory in figure 4.28 has an arrow from valC to the register file. Why not?

A. they left out the arrow to keep the figures simple
B. they use a more complicated a path (through ALU A and valE) from valC to the register file
C. they don't need a path; the immediate value is visible to the register file directly
D. trick question; irmovq doesn't do what the question description says it does

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Spring 2016 Quiz 8

Part 1 of 2 - Pipeline Characteristics

Part 2 of 2 - Pipeline Registers

A generic register has two inputs: a single-bit clock and several-bit data input; it also has one output, a several-bit data output.

A pipeline register has the inputs of a generic register and also two one-bit inputs bubble and stall. We assume that it is never the case that both bubble and stall are 1.

The following questions assume G is a generic register with inputs {G.clock, G.input} and output {G.output}. They ask how to implement a pipeline register with inputs {bubble, stall, clock, input} and output {output} using G.

Spring 2016 Quiz 9

Question 1 of 5

1.0 Points

In the context of chapter 4, a hazard is a characteristic of which of the following?

A. The pipeline implementation
B. The particular instruction(s) executing
C. both of the above
D. none of the above

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Question 2 of 5

1.0 Points

In the context of chapter 4, a dependency is a characteristic of which of the following?

A. The pipeline implementation
B. The particular instruction(s) executing
C. both of the above
D. none of the above

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Question 3 of 5

1.0 Points

Suppose we are executing a program containing instructions: i1, i2, i3, i4, ... etc. Assume all of the instructions run in order and without jumps, stalls, dependencies, or hazards. Assume the five-stage pipeline discussed in the textbook.

If i5 is in the execute (E) stage, what is in memory (M)?

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Question 4 of 5

1.0 Points

Suppose we are executing a program containing instructions: i1, i2, i3, i4, ... etc. Assume all of the instructions run in order and without jumps or stalls. Assume the five-stage pipeline discussed in the textbook.

If we use data forwarding to get i5 through the execute (E) stage, we did which of the following?

A. Kept i5 in E for additional cycles so that the instructions in F and/or D could do some more work first
B. Kept i5 in E for additional cycles so that the instructions in M and/or W could do some more work first
C. Took information from the instructions that were in F and/or D while i5 was in E
D. Took information from the instructions that were in M and/or W while i5 was in E

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Question 5 of 5

1.0 Points

Suppose we are executing a program containing instructions: i1, i2, i3, i4, ... etc. Assume all of the instructions run in order and without jumps or forwarding. Assume the five-stage pipeline discussed in the textbook.

If we use stalling to get i5 through the execute (E) stage, we did which of the following?

A. Kept i5 in E for additional cycles so that the instructions in F and/or D could do some more work first
B. Kept i5 in E for additional cycles so that the instructions in M and/or W could do some more work first
C. Took information from the instructions that were in F and/or D while i5 was in E
D. Took information from the instructions that were in M and/or W while i5 was in E

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Spring 2016 Quiz 10

Question 1 of 5

1.0 Points

If power is lost for 1 millisecond and then restored, which kind of RAM will still have its contents?

A. DRAM
B. SRAM
C. Both
D. Neither

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Question 2 of 5

1.0 Points

Which of the following has the best temporal locality? Consider only data accesses, not instructions.

A. for(j=0; j<10; j+=1) { for(i=0; i<100; i+=1) { a[i] += 1; } }
B. for(j=0; j<100; j+=1) { for(i=j; i<100; i+=1) { a[i] += 1; } }
C. while (true) { for(i=0; i<100; i+=1) { a[i] += 1; } do_a_lot_of_work(); }
D. while (true) { for(i=0; i<10000; i+=1) { a[i] += 1; } }

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Question 3 of 5

1.0 Points

Which of the following has the best spatial locality? Consider only data accesses, not instructions.

A. for(j=0; j<10; j+=1) { for(i=0; i<100; i+=1) { a[i] += 1; } }
B. for(j=0; j<100; j+=1) { for(i=j; i<100; i+=1) { a[i] += 1; } }
C. while (true) { for(i=0; i<100; i+=1) { a[i] += 1; } do_a_lot_of_work(); }
D. while (true) { for(i=0; i<10000; i+=1) { a[i] += 1; } }

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Question 4 of 5

0.5 Points

Question 5 of 5

0.5 Points

Which of the following is blamed on the cache's replacement policy?

A. capacity miss
B. cold miss
C. conflict miss
D. none of the above

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Spring 2016 Quiz 11

Question 1 of 4

1.0 Points

Dirty bits are associated with

A. direct-mapped caches
B. fully-associative caches
C. write-back caches
D. write-through caches
E. all of the above

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Question 2 of 4

1.0 Points

Given a byte-addressable memory with a 4GB address space; and a direct-mapped cache with 64-byte blocks and 16-bit tags; how many lines are there in the cache? Answer as a base-10 integer with no leading 0:

Question 3 of 4

1.0 Points

Suppose two set-associative caches (A and B) have the same total data capacity, same address size, and same block size, but cache A has twice as many lines per set as cache B. Which of the following is true?

A. A stores more metadata (tags, valid bits, etc) than B
B. B stores more metadata (tags, valid bits, etc) than A
C. A has more sets than B
D. B has more sets than A
E. None of the above

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Question 4 of 4

1.0 Points

In a set-associative cache, which of the following does *not* impact the way an address is split into tag, index, and offset?

A. addressable space in memory
B. number of bytes in each block
C. number of lines in each set
D. number of sets in the cache

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Spring 2016 Quiz 12

Question 1 of 4

1.0 Points

For each code snippet below, assume that p and q each points to an array containing the first nine prime numbers (2, 3, …, 23). Select the answer(s) if and only if the code behaves the same both when p and q are aliases and when they are not aliases.

A. for(i=0; i<9; i+=1) p[i] = q[n-i-1];
B. i=0; while(p[q[i]] < 10) i += 1;
C. int tmp = p; p = q; q = tmp;
D. p ^= q; q ^= p; p ^= q;

Question 2 of 4

1.0 Points

Which of the following best describes the intent of "eliminating loop inefficiencies"?

A. If the result of some computation will not change during the loop, don't do it inside the loop
B. Looping overhead is non-trivial, so minimize the number of loop iterations executed
C. Loops take the most time, so focus on optimizing them first
D. Whenever possible, remove loops by replacing them with recursion, goto, or the like

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Question 3 of 4

1.0 Points

Function inlining (described in an aside in section 5.1) is the ultimate solution to reducing procedure calls. In non-recursive code, it is possible to inline *all* procedures and have no procedure call overhead at all. Doing this is a bad idea because (select all that apply)

A. It decreases the ability to re-use variables and/or registers
B. It makes your code long and hard to maintain
C. It results in a loss of temporal locality of code
D. None of the above

Question 4 of 4

1.0 Points

Which of the following does NOT appear to have an unneeded memory reference? Assume the program does some work between the two address accesses.

A. reading from address A followed by reading from address A
B. reading from address A followed by writing to address A
C. writing to address A followed by reading from address A
D. writing to address A followed by writing to address A
E. all of the above suggest unneeded memory references

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Spring 2016 Quiz 13

Question 1 of 6

1.0 Points

Loop unrolling principally reduces what performance cost?

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Question 2 of 6

1.0 Points

"Multiple Accumulators" is listed under "Parallelism," meaning "pipeline parallelism." They help because

A. they reduce hazards
B. they reduce dependencies
C. they improve prediction
D. none of the above themselves, but they enable other kinds of optimizations

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Question 3 of 6

1.0 Points

Which of the following will be fastest?

A. (a + b) + c + d
B. a + (b + c) + d
C. a + b + (c + d)
D. all the same

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Question 4 of 6

1.0 Points

A. your ISA has many registers
B. your ISA has few registers
C. your pipeline is deep
D. your pipeline is shallow

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Question 5 of 6

1.0 Points

Branch misprediction is a bigger problem if

A. your ISA has many registers
B. your ISA has few registers
C. your pipeline is deep
D. your pipeline is shallow

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Question 6 of 6

1.0 Points

Profilers are particularly useful if

A. you are trying to pick the right level of unrolling
B. your program is doing several complicated actions
C. your program's performance is highly dependant on the input
D. all of the above are reasons to profile
E. none of the above are reasons to profile

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Spring 2016 Quiz 14

Part 1 of 2 -

Question 1 of 8

1.0 Points

All of the following are true for either Java or Hardware exceptions, and most are true of both; which one is only true of one of the two?

A. The handlers are outside the normal flow of execution rules
B. The handler can discover where the exception occurred
C. The code that caused the exception can be resumed after handling
D. The handlers are written in software
E. The handler does not have to resolve the exception

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Part 2 of 2 - HW vs Java Excetions

For the following seven hardware exception concepts, pick the matching Java exception concept. Each of the seven answers is the correct answer to one of the seven questions.

Spring 2016 Quiz 15

Question 1 of 5

0.5 Points

Consider two processes A and B. Which of the following is equivalent to the statement "A and B are executing concurrently"?

A. A.startTime < B.endTime && B.startTime < A.endTime
B. A.startTime < B.endTime \|\| B.startTime < A.endTime
C. There exists a time t between max(A.startTime, B.startTime) and min(A.endTime, B.endTime) at which both A and B are working
D. For all t between max(A.startTime, B.startTime) and min(A.endTime, B.endTime), at most one of A and B is working at time t

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Question 2 of 5

0.5 Points

Consider two processes A and B. Which of the following is equivalent to the statement "A and B are executing in parallel"?

A. A.startTime < B.endTime && B.startTime < A.endTime
B. A.startTime < B.endTime \|\| B.startTime < A.endTime
C. There exists a time t between max(A.startTime, B.startTime) and min(A.endTime, B.endTime) at which both A and B are working
D. For all t between max(A.startTime, B.startTime) and min(A.endTime, B.endTime), at most one of A and B is working at time t

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Question 3 of 5

1.0 Points

Signals are how

A. hardware talks to kernel code
B. hardware talks to user code
C. kernel code talks to hardware
D. kernel code talks to user code
E. user code talks to kernel code
F. user code talks to hardware

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Question 4 of 5

1.0 Points

Interrupts are how

A. hardware talks to kernel code
B. hardware talks to user code
C. kernel code talks to hardware
D. kernel code talks to user code
E. user code talks to kernel code
F. user code talks to hardware

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Question 5 of 5

1.0 Points

Traps are how

A. hardware talks to kernel code
B. hardware talks to user code
C. kernel code talks to hardware
D. kernel code talks to user code
E. user code talks to kernel code
F. user code talks to hardware

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Spring 2016 Quiz 16

Question 1 of 5

1.0 Points

Using virtual addresses,

A. the virtual address space always equals the physical address space
B. the virtual address space may be smaller than the physical address space, but not larger
C. the virtual address space may be larger than the physical address space, but not smaller
D. the virtual address space may be either smaller or larger than the physical address space

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Question 2 of 5

1.0 Points

If each PTE is 8 bytes and each page is 4 KB, how large is a single-level page table for 30-bit addresses?

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Question 3 of 5

1.0 Points

A page table's conceptual datatype (implemented by both single- and multi-level page tables) is

A. Map<PhysicalAddress, VirtualAddress>
B. Map<VirtualAddress, PhysicalAddress>
C. Map<PhysicalAddress, Set<VirtualAddress>>
D. Map<VirtualAddress, Set<PhysicalAddress>>

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Question 4 of 5

1.0 Points

A page table entry in a multi-level page table stores metadata (such as a valid bit) and

A. Physical address(es) (or physical page number(s))
B. Virtual address(es) (or virtual page number(s))
C. Physical at some levels, virtual at others

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Question 5 of 5

1.0 Points

To look up an address (not to access the data at the address, just to perform the address translation) using a three-level page table, the MMU needs to access memory

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Spring 2016 Quiz 17

Question 1 of 4

1.0 Points

If we extend the book's comparison between caches and page tables, for a 48-bit virtual address with 4 KB pages and 40-bit physical addresses, how many bits long is the tag? Answer as a normal decimal integer:

Question 2 of 4

1.0 Points

The set index of an address going to a cache is like the _____ of a virtual address going to a page table

A. the virtual page number
B. the physical page number
C. the virtual page offset
D. the physical page offset
E. the page table base register
F. the page table entry

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Question 3 of 4

1.0 Points

Virtual memory can be thought of as using RAM as a cache for disk. Thought of in this way, virtual memory is

A. write-back
B. write-through
C. neither of the above

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Question 4 of 4

1.0 Points

Some page faults generate SIGSEGV (a.k.a. "segfault") and others are handled without any problems. Which of the following can be handled without a SGISEGV?

A. accessing user address space in the page table as the user
B. accessing kernel address space in the page table as the user
C. accessing user address space in the page table as the kernel
D. accessing kernel address space in the page table as the kernel
E. accessing user address space that is not in the page table as the user

Spring 2016 Quiz 18

Part 1 of 1 -

Compare and contrast memory caching (where slow RAM and fast L# caches interact to provide the illusion of a large, fast memory) and virtual memory (where slow disk and fast RAM interact to provide the illusion of large, fast memory). Several questions refer to "the faster store" (meaning the L# cache for caches, the RAM for virtual memory) and the "slower store" (meaning RAM for caches, disk for virtual memory). Assume for these questions that caching is implemented on a computer without virtual memory and virtual memory is implemented on a computer without caching.

The table below summarizes the paragraph above:

	Memory Caching	Virtual Memory
"the faster store"	L# cache	RAM
"the slower store"	RAM	Disk
assumptions:	The computer has no virtual memory	The computer has no memory caching

Anywhere it matters, assume the cache is set-associative and the virtual memory uses multi-level page tables

Spring 2016 Quiz 0

Question 1 of 4

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Spring 2016 Quiz 1

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Spring 2016 Quiz 2

Part 1 of 1 -

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Spring 2016 Quiz 3

Part 1 of 1 -

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Spring 2016 Quiz 4

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Spring 2016 Quiz 5

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Spring 2016 Quiz 6

Part 1 of 1 -

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Spring 2016 Quiz 7

Question 1 of 4

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Spring 2016 Quiz 8

Part 1 of 2 - Pipeline Characteristics

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Part 2 of 2 - Pipeline Registers

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Spring 2016 Quiz 9

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Spring 2016 Quiz 10

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Spring 2016 Quiz 11

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Spring 2016 Quiz 12

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Spring 2016 Quiz 13

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