Readings are sections of the textbook (Computer Systems: A Programmer's Perspective, 3rd Edition) unless otherwise noted.
| Week 1 |
| Tue 15 Jan |
Course Introduction / Compilation Pipeline [ CR: |
screencapture (webm: am pm; browser:
am pm) |
audio only ( am pm)
] Chapter 1 (skim only)
- Semester preview: Layers of abstraction
- Endianness
- Program Memory Layout (Stack, Heap, etc.)
- Compilation Steps and Object Files
| |
| Wed 16 Jan |
Work on getting a working C environment on your own.
The lab will not be staffed.
| |
| Thu 17 Jan |
Brief Assembly Refresher [ CR: |
screencapture (webm: am pm; browser:
am pm) |
audio only ( am pm)
] page 177’s Aside: ATT versus Intel assembly-code formats, Section 3.4.1, 3.5.1, 3.6.1-3, Figure 3.2, 3.3
- Compilation Steps and Object Files (finish)
- AT&T syntax assembly
- X86-64 calling convention
- LEA (load effective address)
- If to assembly
| |
| Week 2 |
| Tue 22 Jan |
Assembly 2 / C [ CR: |
screencapture (webm: am pm; browser:
am pm) |
audio only ( am pm)
] Section 3.6.5, 3.6.7; review section 2 if you need a C refresher
- X86 condition codes
- cmpq versus subq
testq %rax, %rax- SF, ZF
- Loop-to-assembly
- (if time) Jump Tables
- C types
- Truth in C,
&&, ||
- Pointer Arithmetic
- Arrays versus Pointers
| |
| Wed 23 Jan |
| Lab due by end of day |
| Thu 24 Jan |
More C / Bitwise 0 [ CR: |
screencapture (webm: am pm; browser:
am pm) |
audio only ( am pm)
]
- Command Line Tips
struct and typedef structmalloc, free, dynamic arrays- Problematic things in C:
- Unsigned/signed comparision
- Undefined behavior and its consequences
- Bit shifting
| |
| Week 3 |
| Mon 28 Jan |
(add deadline)
| |
| Tue 29 Jan |
Bitwise operators [ : |
screencapture (webm: am pm; browser:
am pm) |
audio only ( am pm)
] Section 2.1.6-7, 2.1.9; review section 2.2 if you need a 2’s complement refresher
- Bit shifting
- Bitwise and/or/xor
- Bit puzzle strategies
- Mask and shift
- Parallelism example: any-bit-set with
&
| Quiz 01 (pre-quiz for week 3) due 10:45 (released 2019-01-26)
|
| Wed 30 Jan |
| bomb HW due at noon
Lab due by end of day |
| Thu 31 Jan |
ISAs and Y86-64 [ : |
screencapture (webm: am pm; browser:
am pm) |
audio only ( am pm)
] Section 4-4.1, p 361 aside “RISC and CISC instruction sets”
- CISC versus RISC
- Y86-64 instruction set
- Y86-64 machine code
| Quiz 02 (post-quiz for week 3) released, due 2019-02-04 23:59
|
| Week 4 |
| Tue 05 Feb |
SEQ part 1 [ : |
screencapture (webm: am pm; browser:
am pm) |
audio only ( am pm)
] Section 4.2.2-3, 4.2.5, 4.3-4.3.1; You may ignore details of HCL syntax for now.
- SEQ components
- Registers generally and the PC
- Instruction and data memory
- Register file
- MUXes
- Simple processors: nop, addq, jmp
| Quiz 03 (pre-quiz for week 4) due 11:15 (released 2019-02-02)
|
| Wed 06 Feb |
| lists in C due at noon
Lab due by end of day |
| Thu 07 Feb |
SEQ part 2 / HCLs [ : |
screencapture (webm: am pm; browser:
am pm) |
audio only ( am pm)
] Section 4.2 (remaining); skim 4.3.2; HCLRS writeup
- mov CPU
- HCLRS intro
- HCLRS built-in components
- Defining register banks
- Wires and wire widths
- MUXes
- Simple processors in HCLRS
| Quiz 04 (post-quiz for week 4) released, due 2019-02-11 23:59
|
| Week 5 |
| Tue 12 Feb |
SEQ part 3 [ : |
screencapture (webm: am pm; browser:
am pm) |
audio only ( am pm)
] Section 4.3.3-4.3.4
- HCLRS continued
- SEQ “stages”
- Setting MUXes
| Quiz 05 (pre-quiz for week 5) due 11:15 (released 2019-02-09)
|
| Wed 13 Feb |
| bit-fiddling HW due at noon
Lab due by end of day |
| Thu 14 Feb |
SEQ part 4 / Pipelining 0 [ : |
screencapture (webm: am pm; browser:
am pm) |
audio only ( am pm)
] Section 4.4-4.4.3
- SEQ stages/MUXes finishing details
- pipelining idea (laundry example)
- latency and throughput
- register tolerances and diminishing pipelining returns
| Quiz 06 (post-quiz for week 5) released, due 2019-02-18 23:59
|
| Week 6 |
| Tue 19 Feb |
Exam review [ CR: |
screencapture (webm: am pm; browser:
am pm) |
audio only ( am pm)
] | |
| Wed 20 Feb |
Exam review in Lab
| HCL2 (irmovq + rrmovq + jmp) due at noon
|
| Thu 21 Feb |
Exam 1
| |
| Week 7 |
| Mon 25 Feb |
(drop deadline)
| |
| Tue 26 Feb |
Pipelining
Reading: Skim sections 4.5.1 to 4.5.3
- Pipelined Datapath and Control
- Structural Hazards
- Pipeline in Execution
| |
| Wed 27 Feb |
| Lab due by end of day |
| Thu 28 Feb |
Data Hazards and Forwarding
- Pipeline Performance
- Data Hazards
- Generating Data Hazard-Free Code in the Compiler
- Stalling the Pipeline
- Implicit Forwarding (Register File, Load/Store Buffer)
- Explicit Forwarding Support
| |
| Week 8 |
| Tue 05 Mar |
Data and Control Hazards
- Pipelined Datapath and Control with Forwarding
- Load-Use Hazard Detection and Forwarding
- Control Hazards
- Generating Control Hazard-Free Code in the Compiler
- Branch Prediction
| |
| Wed 06 Mar |
| HCL4 (seqhw) due at noon
Lab due by end of day |
| Thu 07 Mar |
Branch Prediction
- Static vs. Dynamic Branch Prediction
- Branch Target Buffers and Branch History Buffers
- Bimodal Predictors
- 2-level Local and Correlating Predictors
- Aliasing and Spectre
| |
| Week 9 |
| Tue 12 Mar |
(no class) | |
| Wed 13 Mar |
(no class) | |
| Thu 14 Mar |
(no class) | |
| Week 10 |
| Mon 18 Mar |
(withdraw deadline)
| |
| Tue 19 Mar |
Deeper Pipelines and Superscalar Execution
- More Dynamic Speculation
- Deeper Pipelines
- Superscalar Execution
- VLIW Architectures
- Exposing ILP via the Compiler
- Instruction Scheduling and Loop Unrolling
| |
| Wed 20 Mar |
| HCL6 (pipehw1) due at noon
Lab due by end of day |
| Thu 21 Mar |
Out-Of-Order Execution
- Register Renaming in the Compiler
- Compiler’s perspectives on Code Motion and Scheduling
- Tomasulo’s Algorithm
- Explicit Register Renaming and OOO Execution
- Modern Processors
| |
| Week 11 |
| Tue 26 Mar |
Cache Organization and Management
- Temporal and Spatial Locality
- Memory Hierarchy
- Cache Fundamentals
- Analyzing Cache Performance
- Direct-Mapped and Associative Caches
| |
| Wed 27 Mar |
| HCL8 (pipehw2) due at noon
Lab due by end of day |
| Thu 28 Mar |
Cache Performance
- Cache Parameter Trade-offs
- Handling Stores
- Cache Misses – The 3 C’s
- Compiler-guided Cache Optimizations
- Hardware-based Cache Optimizations
| |
| Week 12 |
| Tue 02 Apr |
Microarchitectural Side Effects / Exam 2 Review
- Example Prefetching Schemes
- Non-Blocking Caches
- Caches in Modern Processors
- EVICT+TIME Attacks
| |
| Wed 03 Apr |
Exam 2 Review in Lab
| |
| Thu 04 Apr |
Exam 2 ...
| |
| Week 13 |
| Tue 09 Apr |
(no class) | |
| Wed 10 Apr |
| Lab due by end of day |
| Thu 11 Apr |
Cache Attacks and SIMD Parallelism
- PRIME+PROBE Attacks
- Introduction to Cache Coherence
- FLUSH+RELOAD Attacks
- Spectre Attacks
- Flynn’s Taxonomy
- Exploiting SIMD Parallelism in Hardware
- Exposing SIMD Parallelism in the Compiler
| |
| Week 14 |
| Tue 16 Apr |
Exceptions 1 [ CR: |
screencapture (webm: am pm; browser:
am pm) |
audio only ( am pm)
] (suggested) 8.1-2
- Data level parallelism examples
- Processes
- Exceptions
- Address spaces
- System calls
| |
| Wed 17 Apr |
| Rotate due at noon
Smooth checkpoint (no SIMD) due at noon
Lab due by end of day |
| Thu 18 Apr |
Exceptions (finish) /Virtual Memory 1 [ CR: |
screencapture (webm: am pm; browser:
am pm) |
audio only ( am pm)
] (suggested) 8.1-2, 9.1-3, 9.6
- Exception type review / terminology note
- Simple page tables
- Splitting addresses
- Page tables in memory
| |
| Week 15 |
| Tue 23 Apr |
Virtual Memory 2
- Multi-Level Page Tables
- Swapping Pages
- Memory Protection in x86
- Segementation
- Case Study: Paging in i386
| |
| Wed 24 Apr |
Lab: work on memory HW
| Smooth due at noon
|
| Thu 25 Apr |
Virtual Memory and Caches
- Journey of a load/store instruction
- Translation Lookaside Buffers
- TLB Organization and Management
- Physical vs. Virtual Caches
| |
| Week 16 |
| Tue 30 Apr |
Final Exam Review
| Memory due by 11:59pm |
| Fri 03 May |
FINAL EXAM
7PM.
Conflict form.
Gilmer 130.
| |
